Abstract: A display control circuit is capable of adjusting backlight intensity according to image content as well as compensating pixel values of frames for power saving and distortion reduction. The display control circuit includes a threshold determining circuit, a pulse width modulation (PWM) control circuit and a pixel value adjusting circuit. The threshold determining circuit determines a threshold according to a reference value by histogramming a to-be-displayed frame. The threshold is smaller than an upper limit of the pixel values, and a proportion of the number of pixel values between the threshold and the upper limit which occupy a total pixel number is lower than the reference value. The PWM control circuit generates a PWM signal for controlling a backlight luminance according to the threshold. The pixel value adjusting circuit adjusts the values of the pixels according to the threshold.

Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Abstract: A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.

Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Abstract: A dot inversion TFT array is provided. The dot inversion TFT array includes: a plurality of data lines; a plurality of dot unit pairs, each including a first dot unit and a second dot unit and coupled to one of the data lines; and a plurality of gate line pairs, each including a first gate line and a second gate line. A predetermined dot unit pair of the dot unit pairs is coupled to a predetermined gate line pair of the gate line pairs, and two horizontally neighboring dot unit pairs of the dot unit pairs are mirror-symmetrical.

Abstract: A backlight control circuit and method thereof are provided to control the backlight of a backlight module so as to enhance the dynamic contrast ratio and save power. The backlight control circuit includes an average luminance detection circuit, a luminance distribution detection unit, a pulse width control circuit and a pulse width modulator. The average luminance detection circuit detects the average luminance of a frame which includes a plurality of pixels; the luminance distribution detection unit detects the pixel luminance distribution of the frame; the pulse width control circuit generates a pulse width control signal according to the average luminance and the pixel luminance distribution of the frame; and the pulse width modulator generates a pulse width modulation (PWM) signal according to the pulse width control signal, so as to control the backlight of the backlight module.

Abstract: A display control circuit is capable of adjusting backlight intensity according to image content as well as compensating pixel values of frames for power saving and distortion reduction. The display control circuit includes a threshold determining circuit, a pulse width modulation (PWM) control circuit and a pixel value adjusting circuit. The threshold determining circuit determines a threshold according to a reference value by histogramming a to-be-displayed frame. The threshold is smaller than an upper limit of the pixel values, and a proportion of the number of pixel values between the threshold and the upper limit which occupy a total pixel number is lower than the reference value. The PWM control circuit generates a PWM signal for controlling a backlight luminance according to the threshold. The pixel value adjusting circuit adjusts the values of the pixels according to the threshold.

Abstract: A memory controller for multiple addressing modes is provided. The memory controller includes a transmitting unit and a control unit. The transmitting unit transmits an identification message to a non-volatile memory. According to whether the non-volatile memory feeds back an acknowledgement message in response to the identification message, the control unit determines an addressing mode to be used for communicating with the non-volatile memory.

Abstract: A dot inversion TFT array is provided. The dot inversion TFT array includes: a plurality of data lines; a plurality of dot unit pairs, each including a first dot unit and a second dot unit and coupled to one of the data lines; and a plurality of gate line pairs, each including a first gate line and a second gate line. A predetermined dot unit pair of the dot unit pairs is coupled to a predetermined gate line pair of the gate line pairs, and two horizontally neighboring dot unit pairs of the dot unit pairs are mirror-symmetrical.

Abstract: A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.

Abstract: A backlight control circuit and method thereof are provided to control the backlight of a backlight module so as to enhance the dynamic contrast ratio and save power. The backlight control circuit includes an average luminance detection circuit, a luminance distribution detection unit, a pulse width control circuit and a pulse width modulator. The average luminance detection circuit detects the average luminance of a frame which includes a plurality of pixels; the luminance distribution detection unit detects the pixel luminance distribution of the frame; the pulse width control circuit generates a pulse width control signal according to the average luminance and the pixel luminance distribution of the frame; and the pulse width modulator generates a pulse width modulation (PWM) signal according to the pulse width control signal, so as to control the backlight of the backlight module.