Abstract: The present disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers alternating with each other along a first direction and a second stack of dielectric layers and isolating layers alternating with each other along the first direction. The semiconductor device further includes an isolating wall between the first stack and the second stack along a second direction perpendicular to the first direction. The isolating wall includes isolating structures extending along the first direction and being aligned along a third direction perpendicular to the first direction and the second direction. The semiconductor device further includes contact structures extending through at least a part of the second stack along the first direction and connecting structures extending through the isolating wall along the second direction.

Abstract: In certain aspects, a memory device includes a stack structure and contact structures. The stack structure includes alternating first layers and first dielectric layers. The contact structure extends into the stack structure in a first direction, and includes a first contact member extending in the first direction, a second contact member connecting to a first end of the first contact member and extending in a second direction intersected with the first direction, and a third contact member extending in the second direction and connecting to the first contact member. The third contact member is located between the first end and a second end of the first contact member.

Abstract: The present disclosure relates to methods, devices, and systems for managing isolating structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device further includes a gate line slit structure extending through the first stack along the second direction, and a first isolating structure including a first portion in the first stack and a second portion in the gate line slit structure. The first portion of the first isolating structure is in contact with an isolating layer of the first stack. A size of the first portion of the first isolating structure is greater than a size of the isolating layer along the second direction.

Abstract: The present disclosure relates to methods, devices, and systems for managing isolating structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device further includes a gate line slit structure extending through the first stack along the second direction, and a first isolating structure extending along the first direction. The first isolating structure includes a first portion in the first stack and a second portion in the gate line slit structure. A size of the first portion is greater than a size of the second portion along the second direction.

Abstract: A memory device includes a stack structure including a plurality of gate lines and a select gate line, a first channel structure extending through the plurality of gate lines along a first direction, a dielectric layer disposed on the first channel structure and the select gate line, and extending along a second direction perpendicular to the first direction, and a conductive layer disposed in the dielectric layer, and the conductive layer in contact with the select gate line.

Abstract: Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes a stack structure with at least one gate line, a select gate layer and at least one channel structure. The at least one gate line includes a first material. The select gate layer includes a second material different from the first material. The at least one channel structure extends through the stack structure and the select gate layer along a first axis. Each channel structure of the at least one channel structure includes a layered structure.