Abstract: A display driving structure includes a drive component and at least a switching component. The drive component is connected to data lines in pixel groups to provide a one-to-one corresponding data signal to each of the sub-pixels through the data lines. A first input terminal of the switching component is configured to receive a p-th row of scanning signals, a second input terminal is configured to receive a (p+1)-th row of scanning signals, a first output terminal is connected to a p-th row of the scan lines in the pixel group, a second output terminal is connected to a (p+1)-th row of the scan lines in the pixel group, and a control terminal is configured to control the conduction sequence of signals in the switching component according to the polarities of the data signals received by adjacent two sub-pixels connected to each column of the data lines.

Abstract: A display panel, a driving method and a display device are disclosed. The display panel is divided into a first area and a second area arranged along a data line direction. Multiple sub-pixels corresponding to a same row of scan line are connected to data lines in one-to-one correspondence. In the first area and second area, each column of sub-pixels is arranged between two adjacent data lines, where the same column of sub-pixels includes multiple sub-pixel groups, each of which includes at least one sub-pixel. Among two adjacent data lines, one data line is connected with the sub-pixels in the odd groups, and the other is connected with the sub-pixels in the even groups. The sub-pixel groups in the first area and the corresponding sub-pixel groups in the second area are axially symmetrical with respect to a boundary line between the first area and the second area.

Abstract: The display device includes: a display panel, having a plurality of pixel assemblies each including a power supply end; a timing control circuit, having a first signal output end configured to output a selection instruction signal, and a second signal output end configured to output a clock signal; and a power circuit, including a voltage generation assembly configured to generate a plurality of step voltages, a voltage selection assembly configured to select at least one step voltage from the plurality of step voltages in response to the selection instruction signal, and a voltage conversion assembly configured to determine a power supply voltage on the basis of the step voltage in response to the clock signal and to output the power supply voltage to the power supply end.

Abstract: The display driving architecture is configured to drive a display panel which includes: a pixel assembly; the pixel assembly includes a driving transistor and a light-emitting assembly; the driving transistor has a first end connected to a first power end and a second end connected to an anode of the light-emitting assembly, and a cathode of the light-emitting assembly is connected to a second power end; a switching circuit which includes a first switching assembly configured to output a first voltage, a second switching assembly configured to output a second voltage, and a voltage output end; assembly; and the switching circuit outputs, based on high-grayscale data of the pixel assembly, the first voltage to the voltage output end, or outputs, based on low-grayscale data of the pixel assembly, the second voltage to the voltage output end.

Abstract: Provided is a pixel circuit, a display panel, and a display device. The pixel circuit includes a light-emitting unit, a drive unit, and a control unit. A first light-emitting element and a second light-emitting element of the light-emitting unit are electrically connected with the control unit simultaneously. The drive unit is configured to send a data signal to the light-emitting unit to drive the same to emit light.

Abstract: A display panel, a driving method and a display device are disclosed. The display panel is divided into a first area and a second area arranged along a data line direction. Multiple sub-pixels corresponding to a same row of scan line are connected to data lines in one-to-one correspondence. In the first area and second area, each column of sub-pixels is arranged between two adjacent data lines, where the same column of sub-pixels includes multiple sub-pixel groups, each of which includes at least one sub-pixel. Among two adjacent data lines, one data line is connected with the sub-pixels in the odd groups, and the other is connected with the sub-pixels in the even groups. The sub-pixel groups in the first area and the corresponding sub-pixel groups in the second area are axially symmetrical with respect to a boundary line between the first area and the second area.