Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: One or more embodiments of a respirator and a method of making the respirator are disclosed. The respirator can include a harness (60) including first and second straps (62, 64); a mask body (12) including right and left portions (16, 18) on each side of a centerline (24), where the right and left portions (16, 18) are bounded by a perimeter (24) of the mask body (12); a right tab (30) that extends from a right side perimeter segment (26) of the perimeter (24) of the mask body (12) adjacent the right portion (16); and a left tab (40) that extends from a left side perimeter segment (28) of the perimeter of the mask body (12) adjacent the left portion (18). The first strap (62) of the harness (60) is attached to the right and left tabs (30, 40) at first right and left attachment locations (50, 52), and the second strap (64) is attached to the right and left tabs (30, 40) at second right and left attachment locations (54, 56).

Abstract: An artificial knee joint is to be connected between a prosthetic thigh and a prosthetic lower leg. The artificial knee joint includes a knee joint body, a processor mounted in the knee joint body, a damping unit that is coupled to the processor and configurable to provide various damping levels, and an accelerometer coupled to the processor. The accelerometer is configured to measure acceleration subjected to the artificial knee joint, and to generate and transmit a measuring signal according to the measurement to the processor. The processor is configured to control the damping unit to provide one of the damping levels, based on the measuring signal.

Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: A layout method is provided, adaptable to place cell on a chip. Firstly, a chip area is assigned for a floor plan. A global reservation deployment process is then performed to define a plurality of room units to be uniformly distributed on the chip area. Cells are placed on the chip based on the floor plan. The chip area is categorized into at least a high frequency region and a low frequency region according to operation frequencies of the placed cells thereon. A frequency based reservation deployment process is then performed to move one or more room units distributed in the low frequency region toward the high frequency region. A local cell replacement process, a routing and timing analysis are performed. If hotspots are induced, room units around the hotspots are redistributed, and then the steps of local cell replacement, routing and timing analysis are repeated.

Abstract: A layout method is provided, adaptable to place cell on a chip. Firstly, a chip area is assigned for a floor plan. A global reservation deployment process is then performed to define a plurality of room units to be uniformly distributed on the chip area. Cells are placed on the chip based on the floor plan. The chip area is categorized into at least a high frequency region and a low frequency region according to operation frequencies of the placed cells thereon. A frequency based reservation deployment process is then performed to move one or more room units distributed in the low frequency region toward the high frequency region. A local cell replacement process, a routing and timing analysis are performed. If hotspots are induced, room units around the hotspots are redistributed, and then the steps of local cell replacement, routing and timing analysis are repeated.

Abstract: An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According to the preferred embodiment of the routing, the power strips originally bridging the inner elements and the outer power serve as the power source (VDD) and ground (VSS) respectively since the peripheral power ring surrounded the core is removed. Thus the area consumption is reduced as if the surrounded power ring shrinks inwardly. The shared power ring for the adjacent memory cores can also be another aspect for reducing the area.

Abstract: A roof tent for automobiles comprises a rectangular frame including first and second half sub-frames being hinged together, a canopy enclosing tent, a collapsible pole assembly for supporting tent including inverse U-shaped poles each having two equal parts consisting of a vertical and a horizontal poles hinged together, vertical poles further hinged together with first and second sub-frames, a rope assembly having two first ropes connecting second sub-frame and horizontal poles, and two second ropes connecting the vertical poles, an attachment mechanism being slidable on grooved rail of the vehicle, two cushion members for enhancing stability, and four stops releasably secured on grooved rails. This provides a roomy space for allowing at least four persons to sleep therein.