Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

Abstract: A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Abstract: A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Abstract: A latch comparator which includes a preamplifier and a latch circuit. The preamplifier circuit operates amplification on a pair of differential input signals, and generates a pair of pre-amplified differential signals. The latch circuit receives the pre-amplified differential signals, compares the pair of pre-amplified differential signals, and generates a pair of latched comparison signals. The latch circuit includes a latch and a switch circuit. First and second input terminals of the latch receive the pre-amplified differential signals. The switch circuit includes a switch coupling between one of the first and second input terminals of the latch and the preamplifier circuit. The switch receives one of the pair of latched comparison signals as a control signal, and is switched in response to the one of the latched comparison signal.

Abstract: A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.

Abstract: A latch comparator which includes a preamplifier and a latch circuit. The preamplifier circuit operates amplification on a pair of differential input signals, and generates a pair of pre-amplified differential signals. The latch circuit receives the pre-amplified differential signals, compares the pair of pre-amplified differential signals, and generates a pair of latched comparison signals. The latch circuit includes a latch and a switch circuit. First and second input terminals of the latch receive the pre-amplified differential signals. The switch circuit includes a switch coupling between one of the first and second input terminals of the latch and the preamplifier circuit. The switch receives one of the pair of latched comparison signals as a control signal, and is switched in response to the one of the latched comparison signal.

Abstract: A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.