Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.

Abstract: A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.

Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.

Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.

Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.