Abstract: FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through the FIFO memory device. In particular, the diagnostic bits identify all cases of whether the data word includes a corrected or uncorrected error, is without error or is unchecked for errors because the data word did not pass through error detection and correction circuitry within the FIFO memory device.

Abstract: FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a relative queue priority between the first and second request signals. Additional steps are performed to transfer the first arbitration results into a third clock domain that is asynchronously timed relative to the first and second clock domains. The transfer operation may include arbitrating the first arbitration results in a third clock domain to obtain second arbitration results that confirm or correct the first arbitration results.

Abstract: An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration results identify a relative queue priority between the first and second request signals. Additional steps are performed to transfer the first arbitration results into a third clock domain that is asynchronously timed relative to the first and second clock domains. The transfer operation may include arbitrating the first arbitration results in a third clock domain to obtain second arbitration results that confirm or correct the first arbitration results.

Abstract: FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.

Abstract: An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.