Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed.

Abstract: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A method for controlling the top width of a trench. A conductive layer is formed on the trench over the substrate, forming an interlayer over a part thereof, above the conductive layer. A sacrifice layer is formed on the trench sidewall above the interlayer, and the interlayer is removed to expose the trench sidewall above the conductive layer and the sacrifice layer, such that the exposed trench sidewalls are oxidized. Thus, the sacrifice layer on the trench sidewall reduces the top width of the trench. In the oxidization process, silicon oxide is formed on the sacrifice layer and the exposed trench sidewall, such that upper width of the trench will is not increased during subsequent wet etching.

Abstract: A method for controlling the top width of a trench. A conductive layer is formed on the trench over the substrate, forming an interlayer over a part thereof, above the conductive layer. A sacrifice layer is formed on the trench sidewall above the interlayer, and the interlayer is removed to expose the trench sidewall above the conductive layer and the sacrifice layer, such that the exposed trench sidewalls are oxidized. Thus, the sacrifice layer on the trench sidewall reduces the top width of the trench. In the oxidization process, silicon oxide is formed on the sacrifice layer and the exposed trench sidewall, such that upper width of the trench will is not increased during subsequent wet etching.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (?-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.

Abstract: A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (?-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.

Abstract: A method for controlling the top width of a trench. A conductive layer is formed on the trench over the substrate, forming an interlayer over a part thereof, above the conductive layer. A sacrifice layer is formed on the trench sidewall above the interlayer, and the interlayer is removed to expose the trench sidewall above the conductive layer and the sacrifice layer, such that the exposed trench sidewalls are oxidized. Thus, the sacrifice layer on the trench sidewall reduces the top width of the trench. In the oxidization process, silicon oxide is formed on the sacrifice layer and the exposed trench sidewall, such that upper width of the trench will is not increased during subsequent wet etching.

Abstract: The present invention provides a method for performing a pre-amorphization implant which reduces damage to the resist protect oxide layer and reduces leakage current between the gate and substrate. Two novel approaches are provided, both of which use a photoresist mask to protect the RPO from implant damage during PAI. In the first approach, the PAI is performed immediately after RPO etching to form contact openings. Thus the original photoresist mask is still on the RPO. In the second approach, the photoresist mask is re-formed prior to PAI to protect the RPO from implant damage.

Abstract: An integrated check valve/strainer-filter assembly that combines a check valve with a strainer-filter assembly in a compact structure is provided. The novel assembly provides the benefits of floor space savings and low maintenance costs. A strainer-filter element may be mounted in a removable strainer-filter housing to provide easy access to the element for cleaning or replacement. The check valve may be installed at one of three desirable positions thus affording additional flexibility of the present invention novel apparatus.

Abstract: A method for forming an anti-reflective-coating(ARC) layer is described. This ARC layer performs not only in its capacity to reduce reflections from its subjacent metal layer during the metal patterning photoresist exposure, but also serves as an effective etch inhibitor during subsequent via etching. Of particular importance is the ability provided by this ARC layer to sustain its etch resistance during considerable over etching such as is required when vias of different depths are to be opened. The ARC layer differs from the conventional titanium nitride ARC layer in that it has a base layer of titanium below the titanium nitride portion. It is this titanium layer and an optional intermediate Ti rich layer that sustains the over etch. Additionally, the titanium forms an improved bonding with the metal beneath providing reduced via contact resistance and greater via stability and consistency.