Patents by Inventor Jiann-Liang Chen

Jiann-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950771
    Abstract: The present invention provides a supporting hook structure, comprising a sleeve, a fixing rod, a first limit unit, a hook and a fixing device. The fixing rod is connected to the side surface of the sleeve. The hook body is connected to one end of the sleeve. The first limit unit is arranged on the side surface of the sleeve and adjacent to the hook body. The first limit unit makes the hook body rotates with the axis direction of the sleeve as a rotation axis. The fixing device is connected to the other end of the sleeve to fix the rotating position of the hook body. Through the above, the hook part enters the proximal thigh from a surgical entrance and the hook part rotates to make the hook part abut against the proximal femur to complete the positioning and fixation of the femur hook structure to the femur.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED ORTHOPEDIC CORPORATION
    Inventors: Yan-Shen Lin, Jiann-Jong Liau, Yu-Liang Liu, Teh-Yang Lin, Wen-Chuan Chen
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Publication number: 20240096867
    Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 10984288
    Abstract: A malicious software recognition apparatus and method are provided. The malicious software recognition apparatus stores a training dataset, which includes a plurality of network flow datasets. Each network flow dataset corresponds to one of a plurality of software categories, and the software categories include a plurality of malicious software categories. The malicious software recognition apparatus tests a malicious software recognition model and learns that a plurality of recognition accuracies of a subset of the malicious software categories are low, determines that an overlap degree of the network flow datasets corresponding to the subset is high, updates the software categories by combining the malicious software categories corresponding to the subset, updates the training dataset by integrating the network flow datasets corresponding to the subset, trains the malicious software recognition model according to the updated training dataset.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 20, 2021
    Assignee: Institute For Information Industry
    Inventors: Wei-Chao Hsu, Ying-Tsun Ke, Jiann-Liang Chen, Yu-Hung Chen, Yan-Ju Chen
  • Publication number: 20200125896
    Abstract: A malicious software recognition apparatus and method are provided. The malicious software recognition apparatus stores a training dataset, which includes a plurality of network flow datasets. Each network flow dataset corresponds to one of a plurality of software categories, and the software categories include a plurality of malicious software categories. The malicious software recognition apparatus tests a malicious software recognition model and learns that a plurality of recognition accuracies of a subset of the malicious software categories are low, determines that an overlap degree of the network flow datasets corresponding to the subset is high, updates the software categories by combining the malicious software categories corresponding to the subset, updates the training dataset by integrating the network flow datasets corresponding to the subset, trains the malicious software recognition model according to the updated training dataset.
    Type: Application
    Filed: November 20, 2018
    Publication date: April 23, 2020
    Inventors: Wei-Chao HSU, Ying-Tsun KE, Jiann-Liang CHEN, Yu-Hung CHEN, Yan-Ju CHEN
  • Patent number: 7881226
    Abstract: Disclosed is a managing architecture and diagnostic method for remote configuration of heterogeneous local networks, which includes at least one sub-network agent, a local area network (LAN) management module and a remote LAN module. Each sub-network agent manages its sub-networks via its own management protocol, and collects the sub-networks' information. The LAN management module receives the requests from heterogeneous local networks via these sub-network agents, and converts the information associated with each request into a common information model (CIM) to seek a solution for each request. The remote LAN module receives the unsolved requests from the LAN management module via a channel, configures the heterogeneous local networks and uses compatible interface at a remote side to accomplish the management and diagnosis for the heterogeneous local networks.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Jiann-Liang Chen, Hsi-Feng Lu, Bing-Jie Huang, Kuo-Chen Lien
  • Publication number: 20090034424
    Abstract: Disclosed is a managing architecture and diagnostic method for remote configuration of heterogeneous local networks, which includes at least one sub-network agent, a local area network (LAN) management module and a remote LAN module. Each sub-network agent manages its sub-networks via its own management protocol, and collects the sub-networks' information. The LAN management module receives the requests from heterogeneous local networks via these sub-network agents, and converts the information associated with each request into a common information module (CIM) to seek a solution for each request. The remote LAN module receives the unsolved requests from the LAN management module via a channel, configures the heterogeneous local networks and uses compatible interface at a remote side to accomplish the management and diagnosis for the heterogeneous local networks.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 5, 2009
    Inventors: Jiann-Liang Chen, Hsi-Feng Lu, Bing-Jie Huang, Kuo-Chen Lien