Patents by Inventor Jiann-Neng Chen

Jiann-Neng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6515512
    Abstract: A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer characteristic between the input and the output. A capacitive element has a first node coupled to the input of the non-inverting circuit and a second node arranged to receive the digital input signal. A resistive element is coupled between the input and the output of the non-inverting circuit. The re-referencing circuit further includes a transient correcting circuit having a first input coupled to a substantially DC level of the first logic environment, a second input coupled to a substantially DC level of the second logic environment, and an output coupled to the input of the non-inverting circuit. The transient correcting circuit applies transient DC differences between the two environments to cancel the effects of transients in the digital input signal.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: February 4, 2003
    Assignee: Teradyne, Inc.
    Inventor: Jiann-Neng Chen
  • Publication number: 20020057107
    Abstract: A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer characteristic between the input and the output. A capacitive element has a first node coupled to the input of the non-inverting circuit and a second node arranged to receive the digital input signal. A resistive element is coupled between the input and the output of the non-inverting circuit. The re-referencing circuit further includes a transient correcting circuit having a first input coupled to a substantially DC level of the first logic environment, a second input coupled to a substantially DC level of the second logic environment, and an output coupled to the input of the non-inverting circuit. The transient correcting circuit applies transient DC differences between the two environments to cancel the effects of transients in the digital input signal.
    Type: Application
    Filed: January 4, 2002
    Publication date: May 16, 2002
    Inventor: Jiann-Neng Chen
  • Patent number: 6363507
    Abstract: Analog test instrument architecture for performing functional testing of electronic circuit assemblies is disclosed. The analog test instrument includes a plurality of identical channels, each channel including circuitry for driving test stimuli and measuring responses at one node of a circuit assembly under test. The driver and measurement circuitry in each channel implement functions that traditionally have been implemented in a test system using discrete instruments. The analog test instrument further includes a master clock reference, which is used for synchronizing the operation of the driver and measurement circuits. Each channel further includes triggering circuitry for distributing trigger events within the channel and to the other channels; and, an input buffer, which is shared by the measurement circuits in the channel. The synchronized operation, distributed trigger events, and shared input buffers are used to improve the correlation of measurements made during functional testing.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: March 26, 2002
    Assignee: Teradyne, Inc.
    Inventors: Eric L. Truebenbach, Jiann-Neng Chen, Richard P. Davis, John J. Arena, Teresa P. Lopes, David J. Lind
  • Patent number: 6194910
    Abstract: A tester that is capable of performing voltage measurements on electronic circuits is disclosed. The tester includes voltage measurement circuitry with an input, a plurality of gain stages, and switching circuitry coupled between the input and the gain stages. The switching circuitry includes a plurality of diodes, and a portion of the gain stages includes current-to-voltage converters. Each diode is coupled to a respective current-to-voltage converter. By applying different bias voltages to the respective current-to-voltage converters, the diodes can be made to conduct current for different ranges of voltages at the input. The output of each current-to-voltage converter is proportional to a respective voltage range.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: February 27, 2001
    Assignee: Teradyne, Inc.
    Inventors: Richard P. Davis, Jiann-Neng Chen
  • Patent number: 5631572
    Abstract: An apparatus and method are disclosed for testing connections between printed circuit boards and components mounted thereon. A conductive loop is formed by forward biasing a parasitic diode that is inherently present between an integrated circuit (IC) lead and the ground plane of the IC. A magnetic field is created by an antenna mounted above the component to be tested. When the antenna is energized by an RF source, a voltage is induced in the conductive loop if the loop is continuous, i.e., if all of the connections are properly made. The voltage in the loop is measured and compared to a selected threshold to produce a pass/fail indication. This tester may be implemented as an improvement to a standard type of "bed-of-nails" printed circuit board tester. The antenna may be implemented as an array of spiral loop antennas, with adjacent antennas producing magnetic fields that are 90 degrees out of phase with each other.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: May 20, 1997
    Assignee: Teradyne, Inc.
    Inventors: Timothy W. Sheen, Jiann-Neng Chen, Stephen A. Cohen, Michael A. Baglino, Joseph F. Wrinn
  • Patent number: 4734637
    Abstract: Apparatus for precisely and quickly measuring the length of a line under test to an electrical discontinuity of the line, the apparatus including an edge generator for providing an edge to one end of the line, a reflection detector for detecting the edge reflection returning from the discontinuity to the one end and triggering the edge generator to provide an edge at a fixed time after detecting the edge reflection so as to cause the edge generator to repeatedly provide the edges at a frequency related to the propagation delay in the length of line, and a frequency measurer connected to measure the frequency.
    Type: Grant
    Filed: April 16, 1986
    Date of Patent: March 29, 1988
    Assignee: Teradyne, Inc.
    Inventors: Jiann-Neng Chen, Stephen A. Cohen
  • Patent number: 4660197
    Abstract: Quickly synchronizing adjustable delay circuits for a multiple channel tester by using a timing pulse that has reached the end of a given path in the tester to trigger the following timing pulse of a timing generator, thereby providing oscillating timing pulses having an associated frequency related to the propagation delay associated with the particular path, comparing the associated frequency with a reference frequency and adjusting a delay provided in the path until the associated frequency matches a desired frequency.
    Type: Grant
    Filed: November 1, 1985
    Date of Patent: April 21, 1987
    Assignee: Teradyne, Inc.
    Inventors: Joseph F. Wrinn, Lawrence Heller, Jiann-Neng Chen, Jacqueline N. Brenner