Patents by Inventor Jiann-Tseng Huang
Jiann-Tseng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9177668Abstract: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.Type: GrantFiled: June 11, 2013Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Chieh Lin, Jiann-Tseng Huang, Wei-Li Liao, Kuoyuan Hsu
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Patent number: 9053780Abstract: In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage.Type: GrantFiled: April 1, 2013Date of Patent: June 9, 2015Assignee: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY, LTD.Inventors: Kuoyuan Hsu, Po-Hung Chen, Jiann-Tseng Huang, Subramani Kengeri
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Patent number: 8824234Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.Type: GrantFiled: February 20, 2013Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
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Patent number: 8767498Abstract: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.Type: GrantFiled: October 31, 2011Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiann-Tseng Huang, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Patent number: 8614927Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.Type: GrantFiled: August 27, 2012Date of Patent: December 24, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Jiann-Tseng Huang, Wei-Li Liao
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Publication number: 20130272080Abstract: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Sung-Chieh LIN, Jiann-Tseng HUANG, Wei-Li LIAO, Kuoyuan HSU
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Publication number: 20130155799Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.Type: ApplicationFiled: February 20, 2013Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, David YEN, Wei-Li LIAO, Jiann-Tseng HUANG, Kuoyuan (Peter) HSU
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Patent number: 8467258Abstract: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.Type: GrantFiled: August 30, 2010Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Chieh Lin, Jiann-Tseng Huang, Wei-Li Liao, Kuoyuan Hsu
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Publication number: 20130107603Abstract: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiann-Tseng HUANG, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Patent number: 8432759Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.Type: GrantFiled: June 28, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuoyuan Hsu, Po-Hung Chen, Jiann-Tseng Huang, Subramani Kengeri
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Patent number: 8427857Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.Type: GrantFiled: May 6, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Hung Chen, Sung-Chieh Lin, Kuoyuan Hsu, Jiann-Tseng Huang
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Patent number: 8400860Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.Type: GrantFiled: July 20, 2010Date of Patent: March 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
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Publication number: 20120320700Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.Type: ApplicationFiled: August 27, 2012Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, Kuoyuan (Peter) HSU, Jiann-Tseng HUANG, Wei-Li LIAO
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Patent number: 8270240Abstract: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.Type: GrantFiled: May 20, 2010Date of Patent: September 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Jiann-Tseng Huang, We-Li Liao
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Publication number: 20120081165Abstract: A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiann-Tseng HUANG, Sung-Chieh LIN, Kuoyuan HSU, Po-Hung CHEN
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Publication number: 20120051162Abstract: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Chieh Lin, Jiann-Tseng Huang, Wei-Li Liao, Kuoyuan Hsu
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Publication number: 20120020177Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, David YEN, Wei-Li LIAO, Jiann-Tseng HUANG, Kuoyuan (Peter) HSU
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Publication number: 20110273949Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hung CHEN, Sung-Chieh LIN, Kuoyuan HSU, Jiann-Tseng HUANG
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Publication number: 20110026354Abstract: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.Type: ApplicationFiled: May 20, 2010Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Jiann-Tseng Huang, We-Li Liao
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Publication number: 20100329055Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.Type: ApplicationFiled: June 28, 2010Publication date: December 30, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan HSU, Po-Hung CHEN, Jiann-Tseng HUANG, Subramani KENGERI