Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

Abstract: Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

Abstract: In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

Abstract: Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actual deadlock state may be detected once the potential deadlock state is identified. The detected actual deadlock state may be indicated by generating a signal. The method may comprise initiating recovery from deadlock conditions by generating at least one signal that indicates when data is accepted in response to the indication of the actual deadlock state.

Abstract: In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

Abstract: Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

Abstract: In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

Abstract: Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actual deadlock state may be detected once the potential deadlock state is identified. The detected actual deadlock state may be indicated by generating a signal. The method may comprise initiating recovery from deadlock conditions by generating at least one signal that indicates when data is accepted in response to the indication of the actual deadlock state.

Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: A graphics blending feature for a terminal such as a home communication terminal (HCT) allows an overlay image to be selectively blended with a background image through the use of a chroma key function and one or more alpha control bits. The chroma key function is used to determine whether the overlay will be completely transparent or not, and the one or more alpha control bits are used to look up a larger alpha value used to blend the overlay and background images. By using a small number of alpha control bits to retrieve a larger alpha value for blending, memory requirements per pixel are reduced. The chroma key function may be implemented by comparing each overlay pixel value to a chroma value and, responsive to a match, making the overlay pixel transparent (i.e., no blending occurs). A dithering function is included in various embodiments to smooth out the resulting image.

Abstract: Interpolating a low or medium resolution image to a higher resolution image using a pixel replication and averaging technique. An overlay image having pixels of a first display resolution and a plurality of alpha blending values each indicating the degree of blending with a background image is interpolated to the resolution of the background image. In addition to interpolating pixel values, alpha blending values are themselves interpolated and multiplied by corresponding overlay pixel values prior to being blended with the background image.

Abstract: An improved graphical manipulation technique for a home communication terminal (HCT) includes a linked-list of commands controlling various video operations in an application specific integrated circuit (ASIC). After each command has been implemented by the ASIC, the ASIC proceeds to the next command without interrupting a host processor. Accordingly, the linked-list eliminates the need of the host processor to continually process interrupts at the completion of each instruction. The linked-list command structure aids in intensive video operations including bit block transfers, video capture, and video display.