Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: Display substrate, method for manufacturing the same, and display device are disclosed. The display substrate comprises: a base substrate comprising a display region and a peripheral region located at a periphery of the display region, the display region comprises at least two display sub-regions; the display substrate further comprises scanning lines and sub-pixels, wherein the scanning lines comprise first scanning lines comprising at least two scanning line segments independent from each other, and the at least two scanning line segments are located in different display sub-regions; and the sub-pixels are divided into rows of sub-pixels, the rows of sub-pixels comprise a target row of sub-pixels which is divided into at least two sub-pixel groups located in different display sub-regions, and the scanning line segment is coupled to each sub-pixel in a corresponding sub-pixel group belonging to a same display sub-region.

Abstract: A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

Abstract: A drive control circuit includes an input circuit, a first output circuit and a first output control circuit. An input circuit is configured to control the potentials of a first node and a second node under the control of a signal input terminal and a clock signal terminal. The first output circuit is configured to provide a first power supply signal to a third node under the control of a first node or to provide a second power supply signal to a first output terminal under the control of a second node. The first output control circuit is configured to turn on or turn off the third node and the first output terminal under the control of the first control terminal.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit; the driving signal generation circuit generates the Nth stage of driving signal; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the output control circuit connects the first control node and the second node under the control of a potential of the first node; the voltage control circuit controls a potential of the second node according to the potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the second control node; N is a positive integer.

Abstract: A display substrate and a display device are provided. The display substrate includes a plurality of repeat units. Each of the plurality of repeat units includes one first-color sub-pixel, one second-color sub-pixel pair and one third-color sub-pixel which are arranged in a first direction, the second-color sub-pixel pair includes two second-color sub-pixels arranging in a second direction. Connecting lines of centers of orthographic projections of light-emitting regions of four second-color sub-pixels on the base substrate form a first trapezoid, and at least one edge of the first trapezoid is located outside orthographic projections of light-emitting regions of respective sub-pixels on the base substrate.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: The present disclosure relates to a mask, a mask device and a mask design method. The mask includes: a pattern area, wherein the pattern area includes a plurality of openings, among which adjacent openings are spaced apart by a first rib, and at least one of the plurality of openings has a non-straight side, two first straight sides intersecting with the non-straight side, and a second straight side opposite to the non-straight side and intersecting with the first straight sides; and a second rib located at an edge of the pattern area, wherein the second rib is provided with a cutout for compensating for stretch deformation of the non-straight side, extending lines of the two first straight sides extending toward the second rib along a first direction intersect with the second rib to obtain a first area, and the cutout is located at least within the first area.

Abstract: A display substrate and a display device are provided. The display substrate includes a plurality of repeat units. Each of the plurality of repeat units includes one first-color sub-pixel, one second-color sub-pixel pair and one third-color sub-pixel which are arranged in a first direction, the second-color sub-pixel pair includes two second-color sub-pixels arranging in a second direction. Connecting lines of centers of orthographic projections of light-emitting regions of four second-color sub-pixels on the base substrate form a first trapezoid, and at least one edge of the first trapezoid is located outside orthographic projections of light-emitting regions of respective sub-pixels on the base substrate.

Abstract: A film mask, a manufacturing method thereof, a display panel and a display device are provided. The mask includes a frame and a first align mask. The frame includes two first frame edges extending along a first direction and arranged at intervals along a second direction and two second frame edges extending along the second direction and arranged at intervals along the first direction. The first frame edges and the second frame edges intersect to form a quadrilateral. The first frame edges and the second frame edges include first surfaces and second surfaces which are oppositely disposed. The first surfaces of at least three angles of the four angles are provided with the first align mask. The first align mask is provided with a first align identifier. The first direction intersects with the second direction.

Abstract: A display substrate, a display device, a high-precision metal mask are provided. The display substrate includes first, second, third sub-pixels. In first direction, first and third sub-pixels are alternated to form first sub-pixel rows, second sub-pixels form second sub-pixel rows. In second direction, first and second sub-pixel rows are alternated, first direction is approximately perpendicular to second direction. Two first and two third sub-pixels in two adjacent rows and two adjacent columns form a 2*2 array, in the array, two first sub-pixels are in different rows and different columns, two third sub-pixels are in different rows and different columns, at least one of two first and two third sub-pixels is a pattern where corner is cut off, connection lines of centers of two first and two third sub-pixels form non-square virtual quadrilateral, and second sub-pixel is within virtual quadrilateral.

Abstract: A display substrate, a display device, a high-precision metal mask are provided. The display substrate includes first, second, third sub-pixels. In first direction, first and third sub-pixels are alternated to form first sub-pixel rows, second sub-pixels form second sub-pixel rows. In second direction, first and second sub-pixel rows are alternated, first direction is approximately perpendicular to second direction. Two first and two third sub-pixels in two adjacent rows and two adjacent columns form a 2*2 array, in the array, two first sub-pixels are in different rows and different columns, two third sub-pixels are in different rows and different columns, at least one of two first and two third sub-pixels is a pattern where corner is cut off, connection lines of centers of two first and two third sub-pixels form non-square virtual quadrilateral, and second sub-pixel is within virtual quadrilateral. The display effect can be improved.

Abstract: There is provided a pixel array including a plurality of sub-pixels, which include first sub-pixels, second sub-pixels, and third sub-pixels. The first and the third sub-pixels are alternately arranged along a row direction and form a plurality of first pixel rows, the first and third sub-pixels, which are in a same column, in the plurality of first pixel rows are alternately arranged, and the second sub-pixels are arranged along the row direction and form second pixel rows. Lines sequentially connecting centers of any two of the first sub-pixels and any two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. At least one interior angle of the first virtual quadrilateral is not 90°. At least one of the first, second and third sub-pixels has a corner circularly or rectilinearly chamfered.

Abstract: A driving circuit, a driving method, a pixel circuit, a display panel and a display device are provided. The driving circuit includes a first switching circuit and a scanning signal generation circuit; the first switching circuit is electrically connected to a first gating control line, at least two data output terminals of a source driver and the scanning signal generation circuit, and is configured to write a data signal provided by the at least two data output terminals into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; the scanning signal generation circuit is configured to generate a scanning signal according to the data signal, and output the scanning signal through the scanning signal output terminal.

Abstract: A display panel and manufacturing method thereof, and a display device, the display panel includes a base substrate, a plurality of sub-pixels are arranged on the base substrate, at least part of the sub-pixels in the plurality of sub-pixels includes a light-emitting layer; at least two sub-pixels consecutively arranged in the plurality of sub-pixels constitute one sub-pixel group, in each sub-pixel group of at least part of the sub-pixel group, the light-emitting layers of at least two consecutively arranged sub-pixels are made of a same material and have an integral structure; the at least part of the sub-pixel group includes at least two sub-pixel groups that respectively emit light of different colors.

Abstract: A method for controlling stretching of a mask includes: obtaining actual position information of at least one opening of the mask; determining an actual offset of each opening according to actual position information of the opening and preset position information of a light-emitting region of a sub-pixel corresponding to the opening; determining whether the actual offset of the opening is less than or equal to a theoretical maximum offset of the opening; and in response to determining that the actual offset of the opening is less than or equal to the theoretical maximum offset of the opening, generating a first end command for ending a process of stretching the mask.

Abstract: The present disclosure provides a pixel structure, a display substrate and a display device, and relates to the field of display technology. The pixel structure includes a plurality of sub-pixels located in an imaginary quadrilateral, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel and at least one third color sub-pixel, the imaginary quadrilateral includes a first inner corner and a second inner corner that are opposite to each other, and a third inner corner and a fourth inner corner that are opposite to each other. The first color sub-pixel is located at the first inner corner c1, the second color sub-pixel 22 is located at the second inner corner c2, and at least one third color sub-pixel is located at the third inner corner c3 and the fourth inner corner c4.

Abstract: The present disclosure provides a display substrate and related devices. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.