Patents by Inventor Jianping Yan
Jianping Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090101Abstract: The present disclosure discloses a high-voltage light string controller, including a first power supply module, a main control module, and a protection module. The first power supply module is suitable for being connected to a mains supply to supply power to the main control module; the main control module is suitable for sending a control signal to a light string to turn on or turn off the light string or to switch a color; the protection module is suitable for identifying a magnitude of a current in the first power supply module, converting the current into a detection signal, and then sending the detection signal to the main control module; the main control module is suitable for receiving and judging the detection signal; and when the detection signal exceeds a preset value, the main control module is suitable for sending a control signal to turn off the light string.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Jianping Yan, Xueren Zeng, Qian Xu, Wei Yi, Shiqing Xia
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Patent number: 11859782Abstract: An AC two-wire LED high voltage lamp string with synchronous dimming and color adjustment comprises a high voltage controller and a lamp string group, wherein the high voltage controller comprises a control box, and a first power supply module, a switch control circuit and a first microcontrol unit which are arranged in the control box and connected in sequence; the first power supply module is connected with the switch control circuit and the first microcontrol unit; a second microcontrol unit. The present invention modulates and encodes a high voltage sine wave using the switch control circuit at the controller end and demodulates the sine wave at a bulb end to realize the functions of color change timing, flashing, timing and light control of lamp strings. The lamp strings can be used individually or connected in series and in parallel for use, to satisfy different needs of consumers.Type: GrantFiled: October 28, 2021Date of Patent: January 2, 2024Inventors: Xueren Zeng, Jiawei Li, Rongqu Tang, Jianping Yan, Lizong Hu, Wei Yi, Xiaofeng Tang
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Publication number: 20230027092Abstract: An AC two-wire LED high voltage lamp string with synchronous dimming and color adjustment comprises a high voltage controller and a lamp string group, wherein the high voltage controller comprises a control box, and a first power supply module, a switch control circuit and a first microcontrol unit which are arranged in the control box and connected in sequence; the first power supply module is connected with the switch control circuit and the first microcontrol unit; a second microcontrol unit. The present invention modulates and encodes a high voltage sine wave using the switch control circuit at the controller end and demodulates the sine wave at a bulb end to realize the functions of color change timing, flashing, timing and light control of lamp strings. The lamp strings can be used individually or connected in series and in parallel for use, to satisfy different needs of consumers.Type: ApplicationFiled: October 28, 2021Publication date: January 26, 2023Inventors: Xueren ZENG, Jiawei LI, Rongqu TANG, Jianping YAN, Lizong HU, Wei YI, Xiaofeng TANG
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Publication number: 20120266036Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: Syntest Technologies, Inc.Inventors: Nur A. TOUBA, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
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Patent number: 8230282Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.Type: GrantFiled: June 29, 2011Date of Patent: July 24, 2012Assignee: Syntest Technologies, Inc.Inventors: Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
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Patent number: 8091002Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: June 9, 2010Date of Patent: January 3, 2012Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
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Patent number: 7996741Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.Type: GrantFiled: August 24, 2009Date of Patent: August 9, 2011Assignee: Syntest Technologies, Inc.Inventors: Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
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Publication number: 20110047426Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.Type: ApplicationFiled: August 24, 2009Publication date: February 24, 2011Inventors: Nur A. TOUBA, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
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Publication number: 20100287430Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: June 9, 2010Publication date: November 11, 2010Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng WANG, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
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Publication number: 20100138709Abstract: A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain.Type: ApplicationFiled: September 4, 2009Publication date: June 3, 2010Inventors: Laung-Terng WANG, Michael S. Hsiao, Hao-Jan Chao, Zhigang Jiang, Shianling Wu, Jianping Yan