Abstract: Circuits, systems, methods and software for controlling a power conversion and/or correcting and/or controlling a power factor in such conversion(s). The present invention generally takes a computational approach to reducing or minimizing zero current periods in the critical mode of power converter operation, and advantageously reduces zero current periods in the critical mode of power converter operation, thereby maximizing the power factor of the power converter in the critical mode and reducing noise that may be injected back into AC power lines. The present power factor controller allows for greater design flexibility, reduced design complexity, and reduced resolution and greater tolerance for error in certain parameter measurements useful in power factor correction and/or control.

Abstract: In a method and apparatus for controlling power factor correction in mixed operation modes, a frequency of the input voltage is obtained by detecting the zero crossing points of the input voltage. A peak of the input voltage is obtained by detecting input voltage with 90 degree phase. Thus, the present invention predicts the input voltage by its frequency and peak and the characteristic of the sine wave. A digital signal processor computes the duty and frequency of a boost switch, switching the operation mode of the boost converter among continuous mode, critical mode and discontinuous mode according to input voltage or the load. According to another aspect, the operation is switched to critical mode from the average current mode when a zero current is detected before the charging and recharging cycle of the boost switch is finished.

Abstract: A Decision-Feedback Equalizer (DFE) includes a Maximum Likelihood Sequence Estimator (MLSE) for estimating a symbol sequence. The DFE also includes a signal level decoder, and a delay line having a first plurality of taps being connected to the output of the signal level decoder, and a second plurality of taps being connected to the output of the MLSE. Furthermore, the DFE has an error signal generator having a first input connected to the input of the signal level decoder, and a second input connected to the output of the signal level decoder for adjusting coefficients of the taps. The symbol delay line has been split into two sections with the output of the MLSE being fed to part of the delay line. Because symbols in the delay line are adjusted with the coefficients and fedback to the signal level decoder, the output of the MLSE is able to correct symbols whenever its output is available. In such a symbol updating approach, error propagation in the delay line is avoided during an error event.