Patents by Inventor Jianqing Wen

Jianqing Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7837795
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: November 23, 2010
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Patent number: 7462239
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 9, 2008
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Publication number: 20080026149
    Abstract: Chloropolysilanes are utilized in methods and systems for selectively depositing thin films useful for the fabrication of various devices such as microelectronic and/or microelectromechanical systems (MEMS).
    Type: Application
    Filed: May 24, 2007
    Publication date: January 31, 2008
    Applicant: ASM America, Inc.
    Inventors: Pierre Tomasini, Chantal Arena, Matthias Bauer, Nyles Cody, Ronald Bertram, Jianqing Wen, Matthew Stephens
  • Patent number: 7108748
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 19, 2006
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Publication number: 20060201414
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Application
    Filed: May 12, 2006
    Publication date: September 14, 2006
    Inventors: Paul Brabant, Joe Italiano, Jianqing Wen
  • Publication number: 20060130743
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 22, 2006
    Inventors: Paul Brabant, Joe Italiano, Jianqing Wen
  • Patent number: 7029995
    Abstract: Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: April 18, 2006
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Paul D. Brabant, Keith D. Weeks, Jianqing Wen
  • Publication number: 20050026400
    Abstract: Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
    Type: Application
    Filed: June 9, 2004
    Publication date: February 3, 2005
    Inventors: Michael Todd, Paul Brabant, Keith Weeks, Jianqing Wen
  • Publication number: 20030036268
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Application
    Filed: May 29, 2002
    Publication date: February 20, 2003
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen