Abstract: A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

Abstract: A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

Abstract: The present invention is a method for fabricating a flash memory device. In one embodiment, a gate structure comprising a tunnel oxide layer, a floating gate layer, an oxide layer, and a control gate layer is fabricated on a semiconductor substrate. A rapid thermal oxidation (RTO) process is then performed to repair the tunnel oxide layer.

Abstract: A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.

Abstract: One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

Abstract: One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells.

Abstract: An apparatus for testing a dielectric property of a material constituting the interlayer dielectric of a flash memory device is formed by a layer (122) of the dielectric material disposed throughout a test structure (200) representative of the flash memory device and a plurality of conductors (117A, 117B, 117C) disposed within that layer (122) or a pair of planar conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) deposited such that the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) are substantially parallel to each other and the layer (122) of dielectric material is disposed throughout a test structure (400, 500) so as to separate the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509), the test structure (400, 500) functioning as a capacitor. The apparatus may also test a conductive property of a material constituting the conducting lines of a flash memory device by disposing a conductor (801, 901) through the dielectric material (122).

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240).

Abstract: A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.

Abstract: A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms.

Abstract: A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects.

Abstract: A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction band energy level (408) and the Fermi energy level (412) of the floating gate (404) is extended so as to readily facilitate the movement of electrons from the substrate (406) into the floating gate (404).

Abstract: A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions.

Abstract: A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.

Abstract: In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.

Abstract: The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments.

Abstract: The present invention is a method and system for eliminating voids in a semiconductor device. The method comprises the steps of forming metal lines over a semiconductor substrate, forming a first oxide layer utilizing a high density plasma deposition technique, forming a second oxide layer utilizing a carbon free resin and forming a topside dielectric layer. Through the use of a method in accordance with the present invention, the voids that are created in the dielectric films during conventional semiconductor processing methodology are eliminated. The use of a high density plasma deposition technique provides a more directional deposition that can get between metal lines that are separated by smaller gaps. The dielectric films are thereby strengthened, which increases the reliability of the semiconductor device.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Abstract: The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device.