Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.

Abstract: Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.

Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.

Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.