Patents by Inventor Jian-Wei Chen

Jian-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272557
    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
  • Patent number: 12272622
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.
    Type: Grant
    Filed: May 29, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 12266575
    Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Lee, Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Hsueh-Ju Chen, Zoe Chen
  • Patent number: 12255104
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Patent number: 12254261
    Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Sing Li, Jung-Chan Yang, Ting Yu Chen, Ting-Wei Chiang
  • Publication number: 20250065743
    Abstract: A wireless charging method for charging an underwater moving device is implemented by a charging device. The charging device receives electricity from a cable, and includes a first underwater wireless communication unit, a position holding unit, a first control unit, and a wireless charging transmitter. The underwater moving device includes a second underwater wireless communication unit, a wireless charging receiver, and a rechargeable battery. The first underwater wireless communication unit obtains moving device information by communicating with the second underwater wireless communication unit. The position holding unit holds the underwater moving device at a charging location, and generates a positioning success signal after the underwater moving device is held at the charging location. Upon receiving the positioning success signal, the first control unit controls the wireless charging transmitter to charge the rechargeable battery based on the moving device information.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 27, 2025
    Inventors: Tai-Yu CHEN, Li-Yuan YEH, Jian-Jhih HUANG, Chih-Wei SHEN, Chang-Qi ZHANG
  • Patent number: 12237400
    Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Po-Yuan Wang, Yu-Shih Wang, Chun-Neng Lin, Ming-Hsi Yeh
  • Publication number: 20250062289
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 12230713
    Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Chi-Sheng Lai, Shih-Hao Lin, Jian-Hao Chen, Kuo-Feng Yu
  • Publication number: 20250026019
    Abstract: A robot fish system includes a robot fish, and a light-emitting device emitting a light signal. The robot fish includes a housing, on which first and second light receivers, a driving module and a processor are disposed. The processor is connected to the first and second light receivers and the driving module. The processor controls the driving module to operate in a left-turn mode to make the robot fish turn left when only the first light receiver receives the light signal, in a right-turn mode to make the robot fish turn right when only the second light receiver receives the light signal, in a straight-moving mode to make the robot fish move straight when both the first and second light receivers receive the light signal, and in a random mode to make the robot fish move randomly when none of the first and second light receivers receives the light signal.
    Type: Application
    Filed: December 4, 2023
    Publication date: January 23, 2025
    Inventors: Chang-Qi ZHANG, Li-Yuan YEH, Tai-Yu CHEN, Jian-Jhih HUANG, Chih-Wei SHEN
  • Patent number: 11687065
    Abstract: A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 27, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shau-Yin Tseng, Jian-Wei Chen
  • Publication number: 20220197263
    Abstract: A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shau-Yin TSENG, Jian-Wei CHEN
  • Patent number: 10043882
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20180151685
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Patent number: 9899491
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20170330952
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Application
    Filed: June 15, 2016
    Publication date: November 16, 2017
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Patent number: 9443952
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 13, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Tsen Lu, Chih-Jung Su, Jian-Wei Chen, Shui-Yen Lu, Yi-Wen Chen, Po-Cheng Huang, Chen-Ming Huang, Shih-Fang Tzou
  • Publication number: 20160170552
    Abstract: A processing method for touch signals includes receiving at least one touch signal packet, wherein the at least one touch signal packet is generated in response to operations of at least one object on a touch device, performing a determination process according to at least one of the at least one touch signal packet and an application program being executed in a computer system, and providing at least one first packet to a first driver or providing at least one second packet to a second driver according to a determination result of the determination process, wherein when receiving the at least one first packet, the first driver generates a first command according to the at least one first packet, and when receiving the at least one second packet, the second driver generates a second command according to the at least one second packet.
    Type: Application
    Filed: September 16, 2015
    Publication date: June 16, 2016
    Inventors: Jian-Wei Chen, Ying-Chieh Chuang, Jiun-Hua Chiu
  • Publication number: 20160099179
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 7, 2016
    Inventors: Chun-Tsen Lu, Chih-Jung Su, Jian-Wei Chen, Shui-Yen Lu, Yi-Wen Chen, Po-Cheng Huang, Chen-Ming Huang, Shih-Fang Tzou
  • Patent number: 9024895
    Abstract: The present invention provides a touch pad operable with multi-objects and a method of operating such a touch pad. The touch pad includes a touch structure for sensing touch points of a first and a second object and a controller for generating corresponding touching signals and related position coordinates. Moreover, the controller calculates at least two movement amount indexes according to coordinate differences between these position coordinates, thereby generating a movement amount control signal to control behaviors of a software object.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 5, 2015
    Assignee: Elan Microelectronics Corporation
    Inventors: Wei-Wen Yang, Chuh-Min Liu, Jian-Wei Chen