Abstract: Embodiments of the disclosure provide a method and a device for processing a portrait image, the method includes: acquiring a to-be-processed portrait image; inputting the to-be-processed portrait image into an image processing model, and acquiring a head smear image output by the image processing model, where the image processing model is configured to smear a hair area of a portrait located above a preset boundary in the portrait image, and the image processing model is generated by training a sample data set of a sample portrait image and a sample head smear image corresponding to the sample portrait image; rendering the head smear image with a head effect material to obtain a portrait image added with an effect; and displaying the portrait image added with the effect.

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

Abstract: A method includes providing a type IV semiconductor substrate having a main surface, forming a type III-V semiconductor channel region over the type IV semiconductor substrate, the type III-V semiconductor channel region comprising a two-dimensional carrier gas, forming a type III-V semiconductor lattice transition region between the type IV semiconductor substrate and the type III-V semiconductor channel region, wherein forming the type III-V semiconductor lattice transition region incudes forming a first lattice transition layer over the type IV semiconductor substrate, the first lattice transition layer having a first metallic concentration, forming a third lattice transition layer over the first lattice transition layer, the third lattice transition layer having a third metallic concentration higher than the first metallic concentration, and forming a fourth lattice transition layer over the third lattice transition layer, the fourth lattice transition layer having a fourth metallic lower than the first m

Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.

Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.

Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

Abstract: A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.

Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.