Abstract: The present application relates to the field of microbiological technology, and particularly relates to a viscous polyhydroxyalkanoate, and its preparation and use. The viscous polyhydroxyalkanoate can be produced by fermenting a Pseudomonas strain containing a mutant of PHA polymerase PhaC61-3, and can be used for the preparation of biodegradable products.

Abstract: A data communication interface has a delay-locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link, a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on timing of transitions in a data signal received over a data channel of the data communication link, a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal, and a calibration circuit. The calibration circuit is configured to calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state, recalibrate the delay-locked loop when the clock and data recovery circuit is activated, and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.

Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.