Abstract: The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

Abstract: The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column.

Abstract: The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

Abstract: A single-layered linear neural network based on a cell synapse structure comprising a pre-synapse and a post-synapse, the pre-synapse comprises a plurality of precursor resistors, number of the precursor resistors is m, one end of the precursor resistors in the pre-synapse is jointly connected with an intermediate point, and another end of the precursor resistors is respectively connected with each of a plurality of precursor signal input ends, number of the precursor signal input ends is m; the precursor signal input ends are used for receiving input voltages; the post-synapse comprises a plurality of posterior resistors, number of the precursor resistors is n, one end of the posterior resistors in the post-synapse is jointly connected with the intermediate point, and another end of the posterior resistors is respectively connected with each of a plurality of posterior signal output ends, number of the posterior signal output ends is n; the posterior signal output ends are used for outputting currents.

Abstract: The disclosure provides a voltage-controlled magnetic anisotropic magnetic random access memory. The memory comprises a virtual array, a memory array and a peripheral circuit, wherein the memory array comprises memory cells with X rows and Y columns; the virtual array comprises virtual cells with X rows and one column; the peripheral circuit comprises at least one data sampling-decision-output circuit, the data sampling-decision-output circuit comprises a sensitive amplifier circuit and a logic circuit in series, and are simultaneously connected to the data sampling-decision-output circuit in the peripheral circuit at the same time. By changing the width-length ratio of a differential circuit in the sensitive amplifier circuit and adding the virtual array, the problem that the storage state of the voltage-controlled magnetic anisotropy magnetic random access memory cannot be determined is effectively solved, and the risk of resistance deviation under different process conditions also can be avoided.

Abstract: The present invention discloses a motion detection circuit applied to CIS and a motion detection method.

Abstract: The present invention discloses a motion detection circuit applied to CIS and a motion detection method.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: The disclosure provides a voltage-controlled magnetic anisotropic magnetic random access memory. The memory comprises a virtual array, a memory array and a peripheral circuit, wherein the memory array comprises memory cells with X rows and Y columns; the virtual array comprises virtual cells with X rows and one column; the peripheral circuit comprises at least one data sampling-decision-output circuit, the data sampling-decision-output circuit comprises a sensitive amplifier circuit and a logic circuit in series, and are simultaneously connected to the data sampling-decision-output circuit in the peripheral circuit at the same time. By changing the width-length ratio of a differential circuit in the sensitive amplifier circuit and adding the virtual array, the problem that the storage state of the voltage-controlled magnetic anisotropy magnetic random access memory cannot be determined is effectively solved, and the risk of resistance deviation under different process conditions also can be avoided.

Abstract: A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip.

Abstract: A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: The present invention provides a solar tracker comprising a supporting unit holding a solar panel, a driving unit regulating the position of the supporting unit, an image sensor having incident angle sensitivity characteristic, an identification unit identifying the current incident angle of the sunlight according to the signal output by the image sensor, and a control unit controlling the driving unit to regulate the position of the supporting unit according to the current incident angle to make the sunlight vertically incident upon the solar panel. The micro lens of each pixel in the image sensor only refracts incident light with a certain specific angle to vertically incident upon the photodiode below the micro lens.

Abstract: The present invention provides an image sensor comprising a pixel array module composed of pixel groups, multiple switch control modules, a PFA, a pipelined ADC and a decode module. Each pixel group comprises multiple unit pixels which form at least one unit pixel. Each switch control module corresponds to a row of the pixel array module and includes a first transmission circuit and a second transmission circuit. The PGA process the data outputted by the first and second transmission circuits and the pipelined ADC performs A/D conversion to the data outputted by the PGA. The decode module controls the first and second transmission circuits of each row to alternately read and transmit the unit pixel data, and controls all the first and second transmission circuits to successively output the data of the unit pixels readout thereby to the PGA.

Abstract: The present invention provides an image sensor comprising a pixel array module composed of pixel groups, multiple switch control modules, a PFA, a pipelined ADC and a decode module. Each pixel group comprises multiple unit pixels which form at least one unit pixel. Each switch control module corresponds to a row of the pixel array module and includes a first transmission circuit and a second transmission circuit. The PGA process the data outputted by the first and second transmission circuits and the pipelined ADC performs A/D conversion to the data outputted by the PGA. The decode module controls the first and second transmission circuits of each row to alternately read and transmit the unit pixel data, and controls all the first and second transmission circuits to successively output the data of the unit pixels readout thereby to the PGA.