Abstract: Structures for a resistive random-access memory element and methods of forming a structure for a resistive random-access memory element. The structure comprises an interlayer dielectric layer including a first trench having a sidewall and a second trench having a sidewall adjacent to the sidewall of the first trench. The structure further comprises a first layer on the sidewall of the first trench, a second layer inside the second trench, and a third layer on the sidewall of the second trench. The first layer comprises a first metal, the second layer comprises a second metal, and the third layer comprises a dielectric material. The third layer includes a portion positioned between the first layer and the second layer.

Abstract: A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.

Abstract: An antifuse device has a first contact structure and a second contact structure in a substrate. The first contact structure has a first contact side adjoining a second contact side and forming a first contact corner having an acute angle. The second contact structure is spaced from and not electrically connected to the first contact structure. The antifuse device further includes a first dummy structure in the substrate, adjacent to the first contact structure. The first dummy structure has a first dummy side nearest to and spaced from the first contact side of the first contact structure.

Abstract: An eFuse structure is provided, the structure comprising a first fuse link having a first side. The first fuse link having a first indentation on the first side, the first indentation having a non-linear profile. A first dummy structure may be laterally spaced from the first indentation of the first fuse link.

Abstract: A memory device may be provided. The memory device may include a first electrode including a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having two bottom electrodes and one top electrode. The present disclosure provides a structure including a first bottom electrode having an upper surface, a second bottom electrode having an upper surface, a switching layer on the upper surface of the first electrode and the upper surface of the second electrode, an oxygen enhancement layer on the switching layer, and a top electrode on the oxygen enhancement layer, the top electrode is positioned above the first bottom electrode and the second bottom electrode.

Abstract: A memory device and method of making the same is provided. The memory device comprises a first electrode having a length along a first axis, a second electrode having a length along a second axis that is perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is positioned between a first electrode edge and a second electrode portion. The cross-sections of the first and second electrodes may have a polygonal shape.

Abstract: A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: A memory device may be provided. The memory device may include a first electrode including a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides and a top surface, in which the sides taper towards each other as they meet the top surface, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top surface of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Abstract: A memory device and method of making the same is provided. The memory device comprises a first electrode having a length along a first axis, a second electrode having a length along a second axis that is perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is positioned between a first electrode edge and a second electrode portion. The cross-sections of the first and second electrodes may have a polygonal shape.

Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.

Abstract: A method and system for constructing an evolving ontology database. The method includes: receiving a plurality of data entries; calculating semantic similarity scores between any two of the data entries; clustering the data entries into a multiple current themes based on the semantic similarity scores; selecting, new concepts from the current themes by comparing the current themes with a plurality of previous themes prepared using previous data entries; and updating the evolving ontology database using the new concepts. The semantic score between any two of the data entries are calculated by: semantic similarity score=?i=0nsie?j=0kwj×f j, where si is weight of features sources, fj is a feature similarity between the two of the data entries, wj is a weight of fj, and j, k and n are positive integers.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.

Abstract: A method and system for generating an article of a product. The method includes: receiving a request from a user; when the request include an identification of the product, retrieving traits of the product from a trait database, when the request include keywords, retrieving the traits of the product by comparing the similarity between the keywords and the traits or the synonym of the traits; generating candidate sentences corresponding to the traits; selecting sentences from the candidate sentences, and revising and rearranging the sentences to generate the article.

Abstract: A method and system for constructing an evolving ontology database. The method includes: receiving a plurality of data entries; calculating semantic similarity scores between any two of the data entries; clustering the data entries into a multiple current themes based on the semantic similarity scores; selecting, new concepts from the current themes by comparing the current themes with a plurality of previous themes prepared using previous data entries; and updating the evolving ontology database using the new concepts. The semantic score between any two of the data entries are calculated by: semantic similarity score=?i=0nsie?j=0kwj×f j, where si is weight of features sources, fj is a feature similarity between the two of the data entries, wj is a weight of fj, and j, k and n are positive integers.