Abstract: Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.

Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.

Abstract: Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

Abstract: Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

Abstract: According to embodiments of the present disclosure, a method, an apparatus, a device, and a computer-readable storage medium for determining a category of an entity are provided. The method includes: based on a suffix of the entity, obtaining a suffix feature associated with the suffix; determining one or more candidate categories of the entity based on a name of the entity; and determining a set of categories of the entity based on the one or more candidate categories and the suffix feature.

Abstract: According to embodiments of the present disclosure, a method, an apparatus, a device, and a computer-readable storage medium for determining a category of an entity are provided. The method includes: based on a suffix of the entity, obtaining a suffix feature associated with the suffix; determining one or more candidate categories of the entity based on a name of the entity; and determining a set of categories of the entity based on the one or more candidate categories and the suffix feature.

Abstract: Embodiments of the present disclosure provide a sample processing method, a sample processing device, an apparatus and a computer readable storage medium. The sample processing method includes the following. A feature representation of samples included in a sample set is determined. Each of the samples has a pre-annotated category. A clustering is performed on the samples to determine a cluster including one or more of the samples based on the feature representation. A purity of the cluster is determined based on categories of samples included in the cluster. The purity indicates a chaotic degree of the categories of samples included in the cluster. Filtered samples are determined from the samples included in the cluster based on the purity.