Patents by Inventor Jianyong Lin

Jianyong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162267
    Abstract: The present invention discloses a microminiature image acquisition and processing system package structure and a preparation method thereof. This structure includes optical coated glass, a CMOS chip, a wafer Re-Distribution Layer and a molding layer, the first surface of the CMOS chip is provided with a photosensitive and microlens region and a metal bonding pad, and a through-silicon via is etched in a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface; the wafer Re-Distribution Layer covers the second surface of the CMOS chip and extends to the through-silicon via. The structure and the method of the present invention are integrated with wafer-level package and SIP integrated package technologies to achieve single package of the whole device, thereby greatly reducing the system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference capability.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Applicant: JCET GROUP CO., LTD.
    Inventors: Jianyong Wu, Yaojian Lin, Danfeng Yang, Chen Xu, Wei Yan
  • Publication number: 20240128142
    Abstract: The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Applicant: JCET GROUP CO., LTD.
    Inventors: Shuo Liu, Yaojian Lin, Jianyong Wu, Wei Yan, Jing Zhao
  • Patent number: D1015478
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 20, 2024
    Inventor: Jianyong Lin