Abstract: An SOP for connection to a first feeder in an electricity distribution network, the SOP being configured to, when a feeder connected to the SOP is faulty, apply a diagnostic voltage to the feeder and make current and voltage measurements at the connection of the SOP to the feeder while the diagnostic voltage is being applied.

Abstract: A method includes obtaining range estimates and carrier phase estimates from each of multiple anchors. The method also includes, in response to determining that a trilateration technique is to be performed, (i) obtaining improved range estimates using the carrier phase estimates and (ii) determining a first location estimate of a target device using the trilateration technique and the improved range estimates. The method also includes, in response to determining that a triangulation technique is to be performed, (i) obtaining differential range estimates using the carrier phase estimates and (ii) determining a second location estimate of the target device using the triangulation technique and the differential range estimates. The method also includes combining the first location estimate and the second location estimate to determine an overall location estimate of the target device.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved conductor layers and dielectric layers stacked in a vertical direction, a top-select-gate (TSG) cut structure extending through an upper portion of the stack structure along the vertical direction and a lateral direction perpendicular to the vertical direction, and dummy channel structures extending through a portion of the stack structure along the vertical direction to a bottom of the TSG cut structure. The dummy channel structures are under the TSG cut structure.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: An integrated pressure condensing boiler is provided which relates to the technical field of boilers. The integrated pressure condensing boiler includes a pressure-bearing housing, a heat-exchange furnace arranged in the pressure-bearing housing, a combustion chamber communicating with the heat-exchange furnace and cooling tube groups fixed in the heat-exchange furnace. Heat-exchange medium flows from bottom to top in the pressure-bearing housing and in the cooling tube groups, and exchanges heat with high-temperature flue gas flowing from top to bottom in the heat-exchange furnace, thus achieving a counterflow heat exchanging. The heat-exchange furnace includes a multi-stage heat-exchange chamber with each heat-exchange chamber being cylindrical. The heat-exchange chambers are arranged in sequence from top to bottom to achieve a flue gas diffusing manner that high-temperature flue gas diffuses from center part to periphery and then gathers from periphery to center part.

Abstract: A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.

Abstract: A method of controlling an electricity distribution network, wherein the electricity distribution network is a mesh network including a plurality of loads and there is a voltage-source converter connected to a point in the network. The method comprises, while using the voltage-source converter to try to hold the voltage magnitude constant at said point, establishing a record of how, at said point, the real power flowing between the network and the voltage-source converter varies with variation of the reactive power that the voltage-source converter causes to flow between itself and the network, using a reactive-power value, proportional to the sum of the reactive-power draws of the loads, in order to look up a real-power value from the record, and configuring the voltage-source converter to supply into the network at said point reactive and real power at said reactive- and real-power values, respectively.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.

Abstract: A method of controlling an electricity distribution network, wherein the electricity distribution network is a mesh network including a plurality of loads and there is a voltage-source converter connected to a point in the network. The method comprises, while using the voltage-source converter to try to hold the voltage magnitude constant at said point, establishing a record of how, at said point, the real power flowing between the network and the voltage-source converter varies with variation of the reactive power that the voltage-source converter causes to flow between itself and the network, using a reactive-power value, proportional to the sum of the reactive-power draws of the loads, in order to look up a real-power value from the record, and configuring the voltage-source converter to supply into the network at said point reactive and real power at said reactive- and real-power values, respectively.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes: a memory stack comprising interleaved conductive layers and dielectric layers; a plurality of channel structures extending vertically through the memory stack; a plurality of channel local contacts each located above and in contact with a corresponding one of the plurality of channel structures, and having a metal material; and a slit structure extending vertically through the memory stack and laterally along a first direction to separate the plurality of channel structures. The slit structure comprises a contact. The contact comprises a first contact portion having a semiconductor material and a second contact portion above the first contact portion and having the metal material. An upper end of the second contact portion and upper ends of the plurality of channel local contacts are coplanar.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The slit structure includes a contact including a first contact portion and a second contact portion above the first contact portion and having a different material of the first contact portion. An upper end of the second contact portion of the slit structure is flush with an upper end of the channel local contact.

Abstract: An integrated pressure condensing boiler is provided which relates to the technical field of boilers. The integrated pressure condensing boiler includes a pressure-bearing housing, a heat-exchange furnace arranged in the pressure-bearing housing, a combustion chamber communicating with the heat-exchange furnace and cooling tube groups fixed in the heat-exchange furnace. Heat-exchange medium flows from bottom to top in the pressure-bearing housing and in the cooling tube groups, and exchanges heat with high-temperature flue gas flowing from top to bottom in the heat-exchange furnace, thus achieving a counterflow heat exchanging. The heat-exchange furnace includes a multi-stage heat-exchange chamber with each heat-exchange chamber being cylindrical. The heat-exchange chambers are arranged in sequence from top to bottom to achieve a flue gas diffusing manner that high-temperature flue gas diffuses from center part to periphery and then gathers from periphery to center part.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a dielectric stack including a plurality of first/second dielectric layer pairs over a substrate, forming a plurality of channel structures extending in a lateral direction in a core region of the dielectric stack, forming a staircase structure including a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack, forming a first drain-select-gate (DSG) cut opening extending in the lateral direction in the core region and a second DSG cut opening in the staircase region, and forming a first DSG cut structure in the first DSG cut opening and a second DSG cut structure in the second DSG cut opening.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.

Abstract: An SOP for connection to a first feeder in an electricity distribution network, the SOP being configured to, when a feeder connected to the SOP is faulty, apply a diagnostic voltage to the feeder and make current and voltage measurements at the connection of the SOP to the feeder while the diagnostic voltage is being applied.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.