Patents by Inventor Jianzhou Wu
Jianzhou Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954123Abstract: A data processing method is disclosed, the method comprising: after data synchronization, obtaining data offset of synchronous data related to a data integration task to be performed, the data offset representing deviation of the synchronous data from corresponding source data; determining whether the synchronous data is complete based on the data offset; in response to the synchronous data being complete, performing the data integration task to the synchronous data.Type: GrantFiled: August 24, 2021Date of Patent: April 9, 2024Assignees: Beijing Zhongxiangying Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jifang Duan, Jianzhou Wang, Shaoqing Wu, Decai He, Jianmin Wu
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Patent number: 11709517Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.Type: GrantFiled: March 10, 2021Date of Patent: July 25, 2023Assignee: NXP USA, Inc.Inventors: Jiawei Fu, Jianzhou Wu, Jie Jin, Yikun Mo, Stefano Pietri
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Patent number: 11689199Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.Type: GrantFiled: June 21, 2022Date of Patent: June 27, 2023Assignee: NXP USA, Inc.Inventors: Jianluo Chen, Jianzhou Wu, Yikun Mo
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Publication number: 20220416779Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.Type: ApplicationFiled: June 21, 2022Publication date: December 29, 2022Inventors: Jianluo Chen, Jianzhou Wu, Yikun Mo
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Patent number: 11201605Abstract: A buffer stage for amplifying a clock signal generated by a current controlled oscillator that receives a first current at a first supply voltage from a first current source. The buffer stage comprises an input terminal configured to receive the clock signal; an output terminal configured to output a buffered signal; at least one buffer, coupled between the input and output terminal, configured to receive a second current at a second supply voltage and buffer the clock signal to generate the buffered signal; a clamping circuit that receives the first current and the second current, and generates a first supply voltage and a second supply voltage. The clamping circuit clamps the second supply voltage equal to the first supply voltage.Type: GrantFiled: December 17, 2020Date of Patent: December 14, 2021Assignee: NXP USA, Inc.Inventors: Jianzhou Wu, Jiawei Fu, Yang Wang, Bin Zhang
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Publication number: 20210286389Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.Type: ApplicationFiled: March 10, 2021Publication date: September 16, 2021Inventors: Jiawei Fu, Jianzhou Wu, Jie Jin, Yikun Mo, Stefano Pietri
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Publication number: 20210194467Abstract: A buffer stage for amplifying a clock signal generated by a current controlled oscillator that receives a first current at a first supply voltage from a first current source. The buffer stage comprises an input terminal configured to receive the clock signal; an output terminal configured to output a buffered signal; at least one buffer, coupled between the input and output terminal, configured to receive a second current at a second supply voltage and buffer the clock signal to generate the buffered signal; a clamping circuit that receives the first current and the second current, and generates a first supply voltage and a second supply voltage. The clamping circuit clamps the second supply voltage equal to the first supply voltage.Type: ApplicationFiled: December 17, 2020Publication date: June 24, 2021Inventors: Jianzhou Wu, Jiawei Fu, Yang Wang, Bin Zhang
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Patent number: 10659013Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.Type: GrantFiled: January 1, 2019Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Yang Wang, Jianzhou Wu, Jie Jin, Jiawei Fu
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Publication number: 20190222201Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.Type: ApplicationFiled: January 1, 2019Publication date: July 18, 2019Inventors: Yang Wang, Jianzhou Wu, Jie Jin, Jiawei Fu
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Patent number: 10027312Abstract: A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.Type: GrantFiled: December 1, 2016Date of Patent: July 17, 2018Assignee: NXP USA, INC.Inventors: Yang Wang, Jianzhou Wu, Yizhong Zhang, Hao Zhi, Bin Zhang, Zhengxiang Wang, Yan Huang
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Publication number: 20180069531Abstract: A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.Type: ApplicationFiled: December 1, 2016Publication date: March 8, 2018Inventors: YANG WANG, JIANZHOU WU, YIZHONG ZHANG, HAO ZHI, BIN ZHANG, ZHENGXIANG WANG, YAN HUANG
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Patent number: 9755619Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.Type: GrantFiled: September 4, 2016Date of Patent: September 5, 2017Assignee: NXP USA, INC.Inventors: Hao Zhi, Jie Jin, Yang Wang, Jianzhou Wu
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Patent number: 9705502Abstract: An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.Type: GrantFiled: December 9, 2014Date of Patent: July 11, 2017Assignee: NXP USA, INC.Inventors: Yang Wang, Jie Jin, Jianzhou Wu
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Patent number: 9654091Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.Type: GrantFiled: November 20, 2015Date of Patent: May 16, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Jianzhou Wu, Jie Jin, Yikun Mo, Yang Wang
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Publication number: 20170117880Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.Type: ApplicationFiled: September 4, 2016Publication date: April 27, 2017Inventors: HAO ZHI, JIE JIN, YANG WANG, JIANZHOU WU
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Patent number: 9606771Abstract: A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.Type: GrantFiled: August 18, 2014Date of Patent: March 28, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wangsheng Mei, Yang Wang, Jianzhou Wu, Yan Xiao
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Patent number: 9551749Abstract: Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.Type: GrantFiled: June 18, 2015Date of Patent: January 24, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wanggen Zhang, Huangsheng Ding, Jianzhou Wu
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Patent number: 9548656Abstract: A low voltage ripple charge pump with slew rate control includes a frequency divider, a clock generator, a current mirror, a switching circuit, a diode network, two capacitors, and a comparator. The frequency divider generates a clock signal from an oscillating signal. The clock generator generates first and second clock signals from the clock signal. The current mirror generates first and second current signals using a reference current. The switching circuit generates first and second voltage signals using the first and second clock signals and the first and second current signals. The comparator generates the oscillating signal based on the first and second voltage signals. The capacitors receive the voltage signals and are connected to the diode network for generating an output signal. The charge pump has low output voltage ripple with small filtering capacitance, which is achieved via slew rate control.Type: GrantFiled: April 26, 2016Date of Patent: January 17, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Yang Wang, Jie Jin, Jianzhou Wu, Hao Zhi
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Publication number: 20160373102Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.Type: ApplicationFiled: November 20, 2015Publication date: December 22, 2016Inventors: Jianzhou Wu, Jie Jin, Yikun Mo, Yang Wang
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Patent number: 9458065Abstract: Provided is a gas generating composition with a low combustion temperature, good ignition ability, and a high heat resistance. The gas generating composition includes: (a) a fuel; (b) an oxidizing agent including a basic metal nitrate; (c) a basic metal carbonate; and (d) a binder. The fuel of the component (a) includes melamine cyanurate (MC) and nitroguanidine (NQ), with a ratio (MC/NQ) of contents of MC and NQ being within a range of 0.3 to 1.5. The binder of the component (d) is one or two or more selected from: (d-1) starch, etherified starch, methyl cellulose, hydroxyethyl methyl cellulose, hydroxypropyl methyl cellulose, and hydroxyethyl cellulose; (d-2) poly(vinyl alcohol), polyvinyl ether, polyethylene oxide, polyvinyl pyrrolidone, and polyacrylamide; (d-3) guar gum, etherified guar gum, and tamarind gum.Type: GrantFiled: March 22, 2012Date of Patent: October 4, 2016Assignee: DAICEL CORPORATIONInventors: Syouji Kobayashi, Jianzhou Wu