Abstract: An LCD (Liquid Crystal Display) Device of improvement of flicker upon switching frame rate and method for the same are proposed. The LCD device includes a pixel matrix, a timing controller and a gate driver. The timing controller outputs a first Gate-On-Enable signal to the gate driver, when the LCD device displays frame according to a first frame rate. When the first frame rate is switched to a second frame rate, the timing controller outputs a second Gate-On-Enable signal to the gate driver to cause a charge time of the pixel matrix to be unchanged. It is appreciated that a pulse width of the second Gate-On-Enable signal is equal to a summation of a pulse width of the first Gate-On-Enable signal and an adjusted pulse width.

Abstract: A liquid crystal display (LCD) and a switching voltage controlling circuit thereof are provided. The LCD includes a display panel and a number of gate drivers. The switching voltage controlling circuit includes a current-controlled switch, a transmission line, and a feedback circuit. A first terminal and a second terminal of the current-controlled switch are respectively coupled to a constant voltage and a first terminal of the transmission line. The transmission line is serially coupled to the gate drivers. Each of the gate drivers generates a switching voltage according to a voltage provided by the transmission line and controls pixel units of the display panel. The feedback circuit regulates an amount of a current passing through the current-controlled switch according to a voltage difference between the first terminal and a second terminal of the transmission line. Thereby, color errors occurring between blocks of the display panel can be reduced.

Abstract: A LCD Device of improvement of flicker upon switching frame rate and method for the same are proposed. The LCD device includes a pixel matrix, a timing controller and a gate driver. The timing controller outputs a first Gate-On-Enable signal to the gate driver, when the LCD device displays frame according to a first frame rate. When the first frame rate is switched to a second frame rate, the timing controller outputs a second Gate-On-Enable signal to the gate driver to cause a charge time of the pixel matrix unchanged. It is appreciated that a pulse width of the second Gate-On-Enable signal is equal to a summation of a pulse width of the first Gate-On-Enable signal and an adjusted pulse width.

Abstract: A liquid crystal display (LCD) and a switching voltage controlling circuit thereof are provided. The LCD includes a display panel and a number of gate drivers. The switching voltage controlling circuit includes a current-controlled switch, a transmission line, and a feedback circuit. A first terminal and a second terminal of the current-controlled switch are respectively coupled to a constant voltage and a first terminal of the transmission line. The transmission line is serially coupled to the gate drivers. Each of the gate drivers generates a switching voltage according to a voltage provided by the transmission line and controls pixel units of the display panel. The feedback circuit regulates an amount of a current passing through the current-controlled switch according to a voltage difference between the first terminal and a second terminal of the transmission line. Thereby, color errors occurring between blocks of the display panel can be reduced.

Abstract: A DAC and a source driver using the same, and a driving method for a display device are provided. The DAC comprises a positive polarity resistor string and a negative polarity resistor string. The resistance of each resistor of the positive polarity resistor string is determined based on positive polarity driving voltages. The resistance of each resistor of the negative polarity resistor string is determined based on negative polarity driving voltages. So, the positive and negative polarity driving voltages, which are used for driving the display device, are in symmetric.

Abstract: A display panel driving device capable of reducing crosstalk and a driving method thereof is disclosed. The display panel driving device includes a plurality of source driving units, a NOT gate and a timing controller. The timing controller, through the NOT gate, provides an inversed-polarity control signal for the source driving units. The display panel driving method includes providing a polarity control signal produced by a timing controller for the remaining source driving units, then inverting the polarity and providing the other partial source driving units with the inversed-polarity control signal. The driving device and the driving method enable the polarities of the pixels on a same horizontal scanning line to be neutral to the greatest extent and avoid crosstalk caused by coupling effect between data lines and the common voltage Vcom. Consequently, the present invention significantly improves the display quality of a display panel by reducing crosstalk.

Abstract: An apparatus and method of driving a display panel are provided. The apparatus includes a comparison unit and a source driver. The comparison unit receives and stores a current line data, and compares the current line data with a previous stored line data. When a pixel data within the current line data and another pixel data within the previous line data at the same position are not identical, the comparison unit outputs the pixel data of the current line data, and the source driver latches the pixel data for driving the display panel, which is output from the comparison unit. When the pixel data within the current line data and another pixel data within the previous line data at the same position are not identical, the comparison unit does not output the pixel data, and the source driver drives the display panel in accordance with the previously latched pixel data.

Abstract: An apparatus for digital-to-analog conversion and the method thereof is disclosed, wherein the complete scale-tuned levels of more bits may be presented with an output of less bits. The apparatus comprises a timing controller, a scale-tuned circuit and a digital-to-analog converter. The timing controller receives an a-bit grayscale value, and outputs a selection signal and a b-bit control signal, wherein a, b are both positive integers and a>b>=1. The selection signal has two states: if the grayscale value is less than or equal to 2a?2c, wherein c is equal to a?b, the selection signal is in a first state; and if the grayscale value is equal to 2a?2c+n, wherein n is an integer and 0<n<2c, the selection signal has a probability of n/2c to be in a second state, and has a probability of 1?n/2c to be in the first state.