Abstract: A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.

Abstract: An array substrate has a display area and includes at least one pixel group, at least one pixel circuit group and at least one shift register circuit. The at least one pixel group is disposed in the display area. Each pixel group includes a plurality of pixels arranged in an array. Each pixel circuit group is disposed between two adjacent rows of pixels or two adjacent columns of pixels in a corresponding pixel group. Each pixel circuit group includes at least one pixel driving sub-circuit group. A shift register circuit is disposed between two rows of pixels or two columns of pixels that are different from two rows of pixels or two columns of pixels between which a pixel driving sub-circuit group is disposed.

Abstract: Disclosed are an array substrate, a detection method for the array substrate, and a splicing display panel. In the array substrate, each of pixels (1) includes sub-pixels (01) of at least three colors and a pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) includes at least one inorganic light-emitting diode; a display area (A1) further includes: a positive signal line (Hm) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Dm), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.

Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.

Abstract: A display panel, a method for driving a display panel, and a display apparatus are provided. The display panel includes a first base substrate and a plurality of pixels on one side of the first base substrate. Each pixel includes: a plurality of pixel sub-electrodes independent from each other and configured to form an electric field with an included angle greater than 0 with respect to a direction perpendicular to the first base substrate under control of incompletely same driving signals; a common electrode on a side of the pixel electrode away from the first base substrate; and an electrophoretic liquid layer between the pixel electrode and the common electrode, including a plurality of charged particles therein.

Abstract: Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

Abstract: A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.

Abstract: An array substrate includes M pixel lines and N pixel circuit groups. The M pixel lines are disposed in a display area and arranged in a first direction. The N pixel circuit groups are arranged in the first direction. M is an integer greater than or equal to 2, and N is a positive integer less than M. A pixel circuit group of the N pixel circuit groups is electrically connected to adjacent two pixel lines of the M pixel lines, and the first direction is one of a row direction and a column direction.

Abstract: A shift register includes: an input circuit configured to receive an input signal; a first control circuit configured to control, in response to a second clock signal and a voltage at a second node, a voltage at the first node; a second control circuit configured to control, in response to a first clock signal, the second clock signal, and the voltage at the first node, a voltage at the second node, and control, in response to the second clock signal and the voltage at the first node, a voltage at the fifth node; and an output circuit configured to transmit, in response to an active level at the first node, a second power signal to an output signal terminal, and transmit, in response to an active level at the fifth node, the first power signal to the output signal terminal. All transistors included in the shift register are N-type transistors.

Abstract: An array substrate has a display area and a non-display area including a first bonding region and a fan-out region located between the display area and the first bonding region. The array substrate includes: a plurality of pixel columns disposed in the display area, at least two first power supply input terminals disposed in the first bonding region, and at least two first fan-out structures disposed in the fan-out region. Each pixel column includes light-emitting units. Each first power supply input terminal is connected to multiple pixel columns of the plurality of pixel columns through one first fan-out structure, so as to provide a first power supply signal to the multiple pixel columns. Each first fan-out structure includes a plurality of first conductive units, and each first conductive unit is electrically connected to at least one of the plurality of pixel columns.

Abstract: A drive method for a display panel, wherein the display panel includes a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line, at least one current data line is connected with the first current selection signal line or the second current selection signal line, and at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line; the method includes: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line.

Abstract: An array substrate, a detection method for the array substrate, and a tiled display panel. In the array substrate, each of pixels (1) comprises sub-pixels (01) of at least three colors and a pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) comprises at least one inorganic light-emitting diode; a display area (A1) further comprises: a positive signal line (Hm) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Dm), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.

Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

Abstract: Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

Abstract: Disclosed are a display panel, a control method for the same, and a display device. The display panel includes: M rows and N columns of pixel units, N current data lines sequentially arranged along a row direction, and N time-length data lines sequentially arranged along the row direction. Each pixel unit includes a pixel circuit, the pixel circuit including a current data terminal and a time-length data terminal. An ith column of the current data lines and an ith column of the time-length data lines are respectively located on two sides of an ith column of pixel units, the current data terminals of the pixel circuits of the ith column of pixel units are electrically connected to the ith column of the current data lines.

Abstract: The present application provides a method for detecting a broken fanout wire of a display substrate, and a display substrate, and belongs to the field of display technology. In the method for detecting a broken fanout wire, the display substrate includes a base substrate having first and second surfaces opposite to each other, and a plurality of connection structures disposed at intervals on the first surface; and each connection structure includes first and second pads and a fanout wire electrically connecting the first pad to the second pad. The method for detecting a broken fanout wire includes: forming at least one detection unit, which includes: connecting at least two connection structures in series through a connecting part; and measuring a head and an end of the detection unit to obtain resistance of the detection unit, and determining whether there is a broken fanout wire in the detection unit.

Abstract: An array substrate has a display area and a non-display area including a first bonding region. The array substrate includes: a plurality of pixel columns disposed in the display area, each of the plurality of pixel columns including a plurality of light-emitting units that are arranged in a second direction, the second direction being perpendicular to a direction in which an edge of the display area proximate to the first bonding region extends; and at least three first power supply input terminals disposed in the first bonding region, each first power supply input terminal being connected to at least one pixel column of the plurality of pixel columns, so as to provide a first power supply signal to the at least one pixel column.

Abstract: A display substrate a driving method therefor, and a display apparatus. The display substrate comprises: M rows and N columns of sub-pixels, N data signal lines and a data reset circuit, wherein at least one sub-pixel comprises a pixel circuit; an ith data signal line is connected to pixel circuits in an ith column, where M?1, N?1, and 1?i?N; and the data reset circuit is electrically connected to a data reset control end, a data initial signal end and the N data signal lines, and is configured to provide a signal of the data initial signal end to the N data signal lines under the control of the data reset control end.

Abstract: A pixel driving circuit includes: a driving sub-circuit configured to supply a driving signal to an element to be driven; a detection sub-circuit electrically connected to a detection control signal terminal and a detection node and configured to detect a voltage value of the detection node in response to a detection control signal received at the detection control signal terminal. The detection node is equivalent to a point on a connection line between the driving sub-circuit and the element to be driven.