Abstract: A memory test system including a memory storing non-transitory machine executable instructions configured to generate test patterns. A processor or state machine is configured to execute the machine executable instructions to generate the test patterns. A memory controller receives the test patterns, writes the generated test patterns to a memory being tested, and reads the test patterns from the memory being tested to create read test patterns. A comparator or controller is configured to compare the generated test patterns to the read test patterns and responsive to differences between the generated test patterns and the read test patterns, generate a memory read error. Pass/fail registers may store data and a memory address associated with the memory read error. The test patterns can be stored for a period of time before being read to test the ability of the memory being tested to store the test pattern.