Patents by Inventor Jiaqiang YU

Jiaqiang YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9218203
    Abstract: The present invention discloses a method, an apparatus, and a system for scheduling a processor core in a multiprocessor core system, which relate to the field of multiprocessor core systems, and can meet the demand for real-time network I/O processing, thereby improving the efficiency of the multiprocessor core system. The method for scheduling a processor core in a multiprocessor core system includes: obtaining, in the running process of the multiprocessor core system, a first control parameter, a second control parameter, a third control parameter, and a fourth control parameter; transferring a packet of a data flow that enters the multiprocessor core system to an idle processor core for processing based on the first control parameter, the second control parameter, and the third control parameter; and switching over the processor core in the multiprocessor core system between an interruption mode and a polling mode based on the fourth control parameter.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 22, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jiaqiang Yu, Wei Zheng
  • Patent number: 9075692
    Abstract: Embodiments of the present invention provide a method, a device and a system for activating an on-line patch. The method comprises: positioning an address of a patch function and an entry address of a to-be-patched function; writing, in a middle segment, a long-jump instruction for jumping to the patch function based on the address of the patch function and the entry address of the to-be-patched function, where the middle segment is a storage space, which is located before or after the entry position of the to-be-patched function and can at least store one long-jump instruction; and modifying an instruction at the entry position of the to-be-patched function to a short-jump instruction for jumping to the middle segment, so as to jump to the middle segment after the short jump instruction is executed, and then to jump to and execute the patch function through that instructions in the middle segment are executed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 7, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jiaqiang Yu, Wei Zheng
  • Publication number: 20140115603
    Abstract: The present invention discloses a method, an apparatus, and a system for scheduling a processor core in a multiprocessor core system, which relate to the field of multiprocessor core systems, and can meet the demand for real-time network I/O processing, thereby improving the efficiency of the multiprocessor core system. The method for scheduling a processor core in a multiprocessor core system includes: obtaining, in the running process of the multiprocessor core system, a first control parameter, a second control parameter, a third control parameter, and a fourth control parameter; transferring a packet of a data flow that enters the multiprocessor core system to an idle processor core for processing based on the first control parameter, the second control parameter, and the third control parameter; and switching over the processor core in the multiprocessor core system between an interruption mode and a polling mode based on the fourth control parameter.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Jiaqiang Yu, Wei Zheng
  • Publication number: 20120102476
    Abstract: Embodiments of the present invention provide a method, a device and a system for activating an on-line patch. The method comprises: positioning an address of a patch function and an entry address of a to-be-patched function; writing, in a middle segment, a long-jump instruction for jumping to the patch function based on the address of the patch function and the entry address of the to-be-patched function, where the middle segment is a storage space, which is located before or after the entry position of the to-be-patched function and can at least store one long-jump instruction; and modifying an instruction at the entry position of the to-be-patched function to a short-jump instruction for jumping to the middle segment, so as to jump to the middle segment after the short jump instruction is executed, and then to jump to and execute the patch function through that instructions in the middle segment are executed.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 26, 2012
    Inventors: Jiaqiang YU, Wei Zheng