Abstract: The present disclosure provides a memory chip, a logic chip, a chip stacked structure, and a memory. The memory chip includes m channels, and the m channels are arranged in a first direction in sequence and are symmetrical about a chip axis. Each channel has a channel signal region, and each channel signal region is divided into 2×2 via regions distributed in an array. Areas of m channel signal regions are the same, and distribution positions of conductive via groups in the m channel signal regions are the same.

Abstract: Provided are a memory chip, a logic chip, a chip stack structure, and a memory. In the memory chip, four first transmission structures are arranged symmetrically about a first axis and a second axis; four second transmission structures in each second transmission structure group are arranged symmetrically about the first axis and the second axis; the memory chip receives one first identification signal from each one of the first transmission structures and generates a chip position identification code based on four first identification signals; the memory chip receives one second identification signal from each second transmission structure group and generates a stack position identification code based on B second identification signals.

Abstract: Provided are a memory chip, a chip stacked structure, and a memory. For the memory chip, n via groups in a first region are symmetrical to n via groups in a second region with respect to a first axis, n via groups in a third region are symmetrical to n via groups in a fourth region with respect to the first axis, and the n via groups in the first region are symmetrical to the n via groups in the fourth region with respect to a second axis. For each via group, a first via is symmetrical to a second via with respect to a third axis, a third via is symmetrical to a fourth via with respect to the third axis, and the first via is symmetrical to the fourth via with respect to a fourth axis.

Abstract: A testing method for a blind spot detection system for an automobile includes: applying an electromagnetic interference signal to the tested automobile through an electromagnetic interference signal application device, meanwhile, simulating a static obstacle or a moving obstacle within a detection range through a testing device, and if the blind spot detection system for the tested automobile is activated, determining that the testing is passed. Repeatable and reproducible testing for the electromagnetic safety of the blind spot detection system may be realized.

Abstract: Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.

Abstract: An embodiment of the present disclosure provides an anti-fuse circuit, including: an anti-fuse unit; a programming circuit connected to the anti-fuse unit, and the programming circuit performs programming of the anti-fuse unit according to the programming control signal and the programming signal; the read unit reads the anti-fuse unit to obtain a data signal; the verification control unit controls the electrical connection between the reading unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, when verifying the programming state of the anti-fuse unit. When the anti-fuse circuit verifies the programming state of the anti-fuse unit, it controls the electrical connection between the read unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, to realize real-time verification of programming status.

Abstract: A semiconductor die, a semiconductor device and a method for forming a semiconductor device are provided. The semiconductor die includes: a substrate including a top surface and a bottom surface; and a plurality of pairs of signal via groups independent of each other, a plurality of signal via groups being arranged in the substrate and spaced apart from each other, two signal via groups in each pair of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate, one of the two signal via groups being distributed in a first region arranged on one side of the axis, and another one of the two signal via groups being distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction.

Abstract: The disclosed anti-fuse circuit includes: an anti-fuse unit; a programming circuit, configured to program the anti-fuse unit according to a programming signal; a verification unit, including a first input terminal, a second input terminal and a first output terminal, the programming signal of the anti-fuse unit is the input signal of the first input terminal, and the data signal stored in the anti-fuse unit is the input signal of the second input terminal. The verification unit verifies the programming state of the anti-fuse unit according to the input signals of the first input terminal and the second input terminal, and the first output terminal outputs a verification signal. The anti-fuse circuit does not need to read out the data signal of the anti-fuse unit to a test machine followed by verifying the programming state of the anti-fuse unit. This anti-fuse circuit saves time and enables high verification accuracy.

Abstract: A semiconductor die, a semiconductor device and a method for forming a semiconductor device are provided. The semiconductor die includes: a substrate including a top surface and a bottom surface; and a plurality of pairs of signal via groups independent of each other, a plurality of signal via groups being arranged in the substrate and spaced apart from each other, two signal via groups in each pair of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate, one of the two signal via groups being distributed in a first region arranged on one side of the axis, and another one of the two signal via groups being distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction.

Abstract: Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.

Abstract: A real-time adjustment device for width and thickness of impregnated fiber bundles includes a width and thickness adjustment mechanism and a width measuring laser mechanism. The width and thickness adjustment mechanism is arranged under a filar guide, and is moved vertically by a cylinder. The width and thickness adjustment mechanism has a hollow concave roller and a hollow convex roller arranged vertically. A position of the hollow convex roller is fixed. Vertical positions of the hollow concave roller are controllable. Fibers pass between the hollow concave roller and the hollow convex roller. The width measuring laser mechanism is arranged between the filar guide and a processing workpiece to measure the fiber width in real-time and send the measurement results back to the control system. The position of the hollow convex roller can be adjusted based on the error between the width and the preset value.

Abstract: A TSV test structure includes: a plurality of TSV groups, each TSV group comprising electrically connected TSVs; a power supply circuit, connected with the TSV groups and configured to provide a first voltage or a second voltage to each TSV group; a control circuit, connected to the power supply circuit and configured to provide a first control signal and a second control signal to the power supply circuit, wherein the power supply circuit outputs the first voltage to at least one TSV group according to the first control signal, and outputs the second voltage to at least one TSV group according to the second control signal; and a readout circuit, electrically connected with the plurality of TSV groups and configured to read electrical signals on the plurality of TSV groups after the control circuit provides the first control signal and the second control signal.

Abstract: The present disclosure provides a method for automatic modeling of an architecture based on an architectural drawing, comprising steps of: reading parameter information of the architectural drawing, identifying a category to which any architectural object belongs by acquiring line segments constituting the architectural object and coordinate data of endpoints of the line segments; generating a binary file or a preset number of binary files based on the coordinate data and elevation data of the endpoints of all the line segments of architectural objects belonging to the same category for all storeys of the architectural drawing; optimizing the binary file or the binary files corresponding to the architectural objects belonging to the same category for all the storeys of the architectural drawing; and generating a three-dimensional model of the architecture. The modeling precision and modeling efficiency of the architecture can be improved by adopting the technical solution of the present disclosure.

Abstract: The present disclosure provides a method for automatic modeling of an architecture based on an architectural drawing, comprising steps of: reading parameter information of the architectural drawing, identifying a category to which any architectural object belongs by acquiring line segments constituting the architectural object and coordinate data of endpoints of the line segments; generating a binary file or a preset number of binary files based on the coordinate data and elevation data of the endpoints of all the line segments of architectural objects belonging to the same category for all storeys of the architectural drawing; optimizing the binary file or the binary files corresponding to the architectural objects belonging to the same category for all the storeys of the architectural drawing; and generating a three-dimensional model of the architecture. The modeling precision and modeling efficiency of the architecture can be improved by adopting the technical solution of the present disclosure.