Abstract: An airborne super-continuum 50-band hyperspectral light detection and ranging system comprises an integrated control system, a storage unit, a super-continuum laser system, an optical transmitting system, a reflecting mirror, a scanning system, an optical receiving system, a super-continuum hyperspectral laser detection system, a plane array CCD camera. The operation process includes super-continuum laser system emitting continuous hyperspectral pulsed lasers, performing lasers beam expansion and collimation, emitting it to ground objects, reflecting it, receiving it by the scanning system, transmitting to the optical receiving system, and focusing it into hyperspectral laser detection system for outputting laser hyperspectrum and 3D spatial data, storing laser data in the storage unit with high-resolution multi-spectral data.

Abstract: A for Fast Fourier Transform (FFT) address generator utilizes a butterfly counter to count a butterfly count for each butterfly stage of FFT in numerical sequence; and a stage counter to count a stage count for the butterfly stage of FFT in bit-shifting manner. A data address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a data address according to a first regularized logic function. A twiddle factor address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a twiddle factor address according to a second regularized logic function.

Abstract: A block floating point mechanism for a Fast Fourier Transform processor utilizes a pipelined butterfly processor to receive the source data to be computed, to perform the butterfly computations, and to output the resultant data. A shifter is coupled to the pipelined butterfly processor to receive the resultant data for shifting the resultant data by the largest overflow bit number occurring in the previous stage of butterfly computations. An overflow detector is coupled to the shifter to receive the shifted resultant data for detecting the largest overflow bit number occurring in this stage of butterfly computations, and for sending the detected largest overflow bit number to the shifter.

Abstract: A pipelined multiplier for signed multiplication has a plurality of pipeline stages, each of which includes a row of registers, and a row of operating cells. The operating cells includes a plurality: of AND gates, NAND gates, half adders, and full adders connected to perform the signed multiplication according to the Hatamian-Cash algorithm. The pipelined multiplier is characterized by that the most significant bit of the product is directly obtained from the previous less significant bit of the product.