Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: The present disclosure relates to data processing systems and data processing methods. One example data processing system includes a first computing node, the first computing node includes an artificial intelligence (AI) processor and a reducing operator, the AI processor is configured to perform an AI operation to generate first data of the first computing node, and the reducing operator is configured to perform a reducing operation on second data from a second computing node and the first data to generate a reducing operation result.

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.