Patents by Inventor Jiaw-Ren Shin

Jiaw-Ren Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Deep well implant structure providing latch-up resistant CMOS semiconductor product
    Patent number: 6992361
    Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: January 31, 2006
    Inventors: Jiaw-Ren Shin, Jian-Hsing Lee, Shui-Hung Chen
  • Deep well implant structure providing latch-up resistant CMOS semiconductor product
    Publication number: 20050158938
    Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Jiaw-Ren Shin, Jian-Hsing Lee, Shui-Hung Chen