Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: Disclosed is a method for preparing a lactose-free dairy product containing galactooligosaccharides, comprising a step of using ordinary lactase and ?-galactosidase with transgalactosylation activity, wherein the ordinary lactase decomposes lactose in a dairy product starting material to galactose and glucose; wherein the ?-galactosidase with transgalactosylation activity decomposes lactose in the dairy product starting material to galactose and glucose, and transfers galactose obtained through decomposition onto a hydroxyl group of lactose in the dairy product starting material to achieve conversion to galactooligosaccharides, and optionally, conversion to higher-order galactooligosaccharides; and wherein the galactose obtained through decomposition comprises: 1) galactose obtained by decomposition of lactose by the ordinary lactase; and/or 2) galactose obtained by decomposition of lactose by the ?-galactosidase with transgalactosylation activity.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: A transferring apparatus configured to transfer an electronic component includes a first carrier, a second carrier, an actuator mechanism, and a flexible push generator. The first carrier is configured to carry an objective substrate, and the second carrier is configured to carry a transfer substrate. The actuator mechanism is configured to actuate the first carrier and the second carrier to move close to and away from each other. The flexible push generator is disposed near the first carrier or the second carrier and generates a flexible push to the carried objective substrate or transfer substrate when the first carrier and the second carrier are actuated in a way close to each other. A method of bonding an electronic component and a method for manufacturing a light-emitting diode display are also provided.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: An anti-theft control method for a vehicle comprises determining whether an enabling signal is received by a control device in an anti-theft mode; performing an anti-theft control process by the control device when receiving the enabling signal, wherein the anti-theft control process comprising: detecting a set of position information related to the motor by a position sensor; generating an anti-theft control command according to the set of position information and further outputting a plurality of switching control instructions according to the anti-theft control command by the control device; and outputting a locking command to the motor by a power driving device according to the plurality of switching control instructions for driving the motor to generate a braking force. The locking command comprises a plurality of PWM signals, with one of the plurality of PWM signals has two adjacent periods having the same duty ratio.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.