Abstract: An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.

Abstract: A system and method for a hybrid multimode input device includes a multimode input device capable of a two-dimensional (2D) mode of operation and a three-dimensional (3D) mode of operation. The device includes a two-dimensional (2D) position sensor, a three-dimensional (3D) position sensor, and a processor. The processor is configured to enter a 3D input mode when the processor detects that the input device is in a first orientation, and enter a 2D input mode when the processor detects that the input device is in a second orientation. The 2D input mode is configured to provide 2D position data to a connected computer system, and wherein the 3D input mode is configured to provide 3D position data to the connected computer system.

Abstract: In an embodiment, a display panel circuit structure includes: a display area and an output bonding area located on a side of the display area. The output bonding area includes: a plurality of first bonding pads arranged in parallel at intervals, and a plurality of first connecting lines between corresponding first bonding pads of the first bonding pads. Each of the first bonding pads includes: a first bottom pad, a first middle pad, and a first top pad. The first bottom pad and the first connecting lines are all located at a first metal layer, the first middle pad is located at a second metal layer, the first top pad is located at a transparent, electrically conductive layer, the first metal layer, the second metal layer, and the transparent, electrically conductive layer are stacked in order.

Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.

Abstract: The present disclosure provides an array substrate, a display panel, and an electronic apparatus. The array substrate may include: multiple gate lines each extending along a first linear direction; and multiple data lines each extending along a second linear direction, wherein the multiple gate lines and the multiple data lines are interlaced with each other, the second linear direction is substantially perpendicular to the first linear direction; wherein a notch is defined on the upper edge. By the present disclosure, a wiring path of at least one of the gate lines or at least one of the data lines may avoid the notch. Therefore, a technical problem of uneven distribution of gate lines or data lines and abnormal display image due to the irregular shape of the display panel may be solved.

Abstract: A display panel circuit structure is provided. The display panel circuit structure includes: a display area and an output bonding area located on a side of the display area. The output bonding area includes: a plurality of first bonding pads arranged in parallel at intervals, and a plurality of first connecting lines between corresponding first bonding pads of the first bonding pads. Each of the first bonding pads includes: a first bottom pad, a first middle pad, and a first top pad.

Abstract: An apparatus for a robotic limb includes one or more limb segments connected via one or more joints. The robotic limb may feature one or more dual-reduction quasi-quasi-direct-drive joint actuators that permit the robotic limb to move throughout a scene. The robotic limb may further include an end-effector connected to a free end of the robotic limb with one or more opposable fingers comprising a four bar linkage. The end-effector may include a main actuator that actuates the one or more fingers via the four-bar linkages to complete various tasks.

Abstract: The present application provides a thin film transistor, a method of manufacturing a thin film transistor, and a manufacturing system. The thin film transistor includes a substrate, a buffer layer, an active layer, and a gate insulating layer. A side area of the active layer is doped and modified, so that a surface of the side area is formed as a high resistance area, and then the gate insulating layer is formed by a chemical deposition process, thereby to avoid a weak channel current produced by unintentional electrically conduction of a boundary of the active layer due to a thinner thickness of the gate insulating layer when operating, thereby increasing electrical reliability of the thin film transistor.

Abstract: An array substrate, a display panel, and a manufacturing method for the array substrate are provided, and can effectively decrease issues of damage to an alignment film layer due to photo spacers (especially the main photo spacers) exerted with an external force and scraps generated by the alignment film layer to prevent defective display issues, such as light spots, and further to increase anti-fall reliability of the display panel.

Abstract: A system and method for a hybrid multimode input device includes a multimode input device capable of a two-dimensional (2D) mode of operation and a three-dimensional (3D) mode of operation. The device includes a two-dimensional (2D) position sensor, a three-dimensional (3D) position sensor, and a processor. The processor is configured to enter a 3D input mode when the processor detects that the input device is in a first orientation, and enter a 2D input mode when the processor detects that the input device is in a second orientation. The 2D input mode is configured to provide 2D position data to a connected computer system, and wherein the 3D input mode is configured to provide 3D position data to the connected computer system.

Abstract: A display panel, a display module and an electronic device are provided. The display panel comprises a displaying region, a non-displaying region located on a periphery of the displaying region, wires comprising a first portion located in the displaying region and transmission portions located in the non-displaying region. Line shapes of some of the transmission portions are wave-like line shapes.

Abstract: An apparatus and method for a wall clock AI voice assistant, such as a computing device, is provided herein. The wall-mountable electronic clock includes an optical sensor, a microphone, a digital display and a speaker. The optical sensor captures image data representing at least a portion of a user. The microphone receives an audio input from the user when certain criteria is met, such as when the image data representing at least a portion of the user is captured. The digital display provides visual information to the user provided in response to the captured image data or the audio input. The speaker provides audio information provides from a digital voice assistant in response to the captured image data or the audio input.

Abstract: A display panel, a display device and a method for preparing a low-temperature polysilicon thin film transistor are provided. The method includes: providing a base substrate; forming a semiconducting layer on the base substrate; forming a first insulating layer on the semiconducting layer; forming a first metal layer on the first insulating layer and pattering the first metal layer to obtain a first metal gate layer; forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer and patterning the second metal layer to obtain a second metal gate layer; forming a third insulating layer on the second metal layer; forming a third metal layer on the third insulating layer and patterning the third metal layer to form a source and a drain. The LTPS technology can be applied to the production of large-size panels by adopting the present disclosure.

Abstract: A display panel, a display device and a method for preparing a low-temperature polysilicon thin film transistor are provided. The method includes: providing a base substrate; forming a semiconducting layer on the base substrate; forming a first insulating layer on the semiconducting layer; forming a first metal layer on the first insulating layer and pattering the first metal layer to obtain a first metal gate layer; forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer and patterning the second metal layer to obtain a second metal gate layer; forming a third insulating layer on the second metal layer; forming a third metal layer on the third insulating layer and patterning the third metal layer to form a source and a drain. The LTPS technology can be applied to the production of large-size panels by adopting the present disclosure.

Abstract: The present disclosure discloses a thin film transistor array substrate, a display panel and a display device. The array substrate includes a substrate and an electrostatic discharge circuit layer, and the electrostatic discharge circuit layer is disposed in the non-display area at a side of the substrate and includes a conductive circuit disposed around the display area and electrostatic discharge devices electrically connected with the conductive circuit. The electrostatic discharge device includes a plurality of electrostatic discharge units disposed at intervals, one end of each of the electrostatic discharge units is connected with an edge of the substrate and the other end thereof is connected with the conductive circuit.

Abstract: An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.

Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.

Abstract: The present disclosure provides an array substrate, a display panel, and an electronic apparatus. The array substrate may include: multiple gate lines each extending along a first linear direction; and multiple data lines each extending along a second linear direction, wherein the multiple gate lines and the multiple data lines are interlaced with each other, the second linear direction is substantially perpendicular to the first linear direction; wherein a notch is defined on the upper edge. By the present disclosure, a wiring path of at least one of the gate lines or at least one of the data lines may avoid the notch. Therefore, a technical problem of uneven distribution of gate lines or data lines and abnormal display image due to the irregular shape of the display panel may be solved.