Patents by Inventor Jiaxiang Shi
Jiaxiang Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928071Abstract: Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.Type: GrantFiled: March 27, 2020Date of Patent: March 12, 2024Assignee: MaxLinear, Inc.Inventors: Chuanhua Lei, Jiaxiang Shi
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Patent number: 11886374Abstract: Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.Type: GrantFiled: March 27, 2020Date of Patent: January 30, 2024Assignee: MaxLinear, Inc.Inventors: Chuanhua Lei, Jiaxiang Shi
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Publication number: 20230195633Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.Type: ApplicationFiled: December 29, 2022Publication date: June 22, 2023Inventors: Ritesh BANERJEE, Jiaxiang SHI, Ingo VOLKENING
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Patent number: 11593489Abstract: A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.Type: GrantFiled: December 28, 2018Date of Patent: February 28, 2023Assignee: MaxLinear, Inc.Inventors: Jiaxiang Shi, Chun Feng Hu, Yao Chye Lee, Qiming Wu
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Publication number: 20220214992Abstract: Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.Type: ApplicationFiled: March 27, 2020Publication date: July 7, 2022Inventors: Chuanhua LEI, Jiaxiang SHI
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Publication number: 20220179792Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.Type: ApplicationFiled: November 17, 2021Publication date: June 9, 2022Inventors: Ritesh BANERJEE, Jiaxiang SHI, Ingo VOLKENING
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Patent number: 11354244Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.Type: GrantFiled: November 24, 2015Date of Patent: June 7, 2022Assignee: Intel Germany GmbH & Co. KGInventors: Ritesh Banerjee, Jiaxiang Shi, Ingo Volkening
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Patent number: 10878099Abstract: Anti-fault injection systems and methods are disclosed. An anti-fault injection system includes a processor; a boot ROM configured to store a series of boot instructions executable by the processor; and anti-fault injection controller circuitry. The anti-fault injection controller circuitry is accessible to the processor while the processor is executing the boot instructions. The anti-fault injection controller circuitry includes interrupt/reset circuitry configured to interrupt the processor in response to a trigger and secure boot circuitry. The secure boot circuitry is configured to, in response to being accessed by the processor: determine whether the processor is executing non-secure boot instructions in error; and in response to detecting that the processor is executing non-secure boot instructions in error, provide the trigger to the interrupt/reset circuitry.Type: GrantFiled: November 28, 2017Date of Patent: December 29, 2020Assignee: MaxLinear, Inc.Inventors: Qiming Wu, Jiaxiang Shi
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Publication number: 20200212915Abstract: A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Ravindar Attineni, Sachin Mathur, Jiaxiang Shi
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Publication number: 20200210587Abstract: A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Jiaxiang Shi, Chun Feng Hu, Yao Chye Lee, Qiming Wu
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Patent number: 10700687Abstract: A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.Type: GrantFiled: December 27, 2018Date of Patent: June 30, 2020Assignee: Intel CorporationInventors: Ravindar Attineni, Sachin Mathur, Jiaxiang Shi
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Patent number: 10671551Abstract: Systems, methods, and circuitries adapt a system-on-chip (SoC) for use with different external devices. In one example, an SOC includes a plurality of SoC data lanes configured to conduct data signals between the SoC and an external device interface. The SoC also includes an interface lane adaptor and a device interface including a plurality of interface connectors. The interface lane adaptor circuitry includes a plurality of SoC adaptor connectors connected to the interface connectors; a plurality of external adaptor connectors connected to the SoC data lanes and configured to be connected to the external device interface; a lane selector circuitry configured to connect a selected one of a first or a second SoC adaptor connector to a selected SoC data lane; and a lane configuration circuitry configured to control the lane selector circuitry to connect either the first or the second SoC adaptor connector to the selected SoC data lane.Type: GrantFiled: February 20, 2019Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Jiaxiang Shi, Vinay Sharma, Ingo Volkening
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Publication number: 20180189496Abstract: Anti-fault injection systems and methods are disclosed. An anti-fault injection system includes a processor; a boot ROM configured to store a series of boot instructions executable by the processor; and anti-fault injection controller circuitry. The anti-fault injection controller circuitry is accessible to the processor while the processor is executing the boot instructions. The anti-fault injection controller circuitry includes interrupt/reset circuitry configured to interrupt the processor in response to a trigger and secure boot circuitry. The secure boot circuitry is configured to, in response to being accessed by the processor: determine whether the processor is executing non-secure boot instructions in error; and in response to detecting that the processor is executing non-secure boot instructions in error, provide the trigger to the interrupt/reset circuitry.Type: ApplicationFiled: November 28, 2017Publication date: July 5, 2018Inventors: Qiming Wu, Jiaxiang Shi
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Publication number: 20180173626Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.Type: ApplicationFiled: November 24, 2015Publication date: June 21, 2018Inventors: Ritesh Banerjee, Jiaxiang Shi, Ingo Volkening
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Patent number: 7710979Abstract: There is provided an apparatus and method for ATM bonding. The apparatus comprises a first unit having a first xDSL line connected thereto, a second unit having a second xDSL line connected thereto and a connection between the first unit and the second unit. The first unit is arranged to convert one incoming ATM datastream to a plurality of data and to convert a plurality of incoming data to one ATM data stream. The first unit is arranged to implement the ATM bonding layer of the ATM protocol. The second unit may be arranged to implement one or more of the higher layers.Type: GrantFiled: November 12, 2004Date of Patent: May 4, 2010Assignee: Infineon Technologies AGInventors: Ingo Volkening, Jiaxiang Shi, Chunfeng Hu
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Publication number: 20080147905Abstract: In a first exemplary embodiment of the present invention, a computer system comprises a CPU, and a DMA controller coupled to the CPU for data transfer via a data transfer interrupt mechanism. According to a feature of the present invention, an interrupt coalescing unit couples the DMA controller to the CPU for aggregation of data transfer interrupts generated by the DMA controller, and transfer of data corresponding to the aggregated interrupts, between the CPU and the DMA controller, as a single interrupt.Type: ApplicationFiled: December 15, 2006Publication date: June 19, 2008Applicant: Infineon Technologies AGInventors: Jiaxiang Shi, Ingo Volkening, Bingtao Xu
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Publication number: 20080059674Abstract: An apparatus for chained arbitration of a plurality of inputs for access to a shared resource is provided. The apparatus includes a plurality of levels of arbiters including a first arbitration level having at least one first level arbiter, and a second arbitration level having at least one second level arbiter, the at least one first level arbiter comprising a locker module for generating a lock request signal to the at least one second level arbiter after locking one of the plurality of inputs, the at least one second level arbiter comprising a grant module for generating a grant signal to the at least one first level arbiter in response to the lock signal, whereby upon receipt of the lock signal the at least one first level grants access to the at least one second level arbiter for the locked one of the plurality of inputs.Type: ApplicationFiled: September 1, 2006Publication date: March 6, 2008Inventors: Jiaxiang Shi, Hong Lee Koo, Juraj Povazanec
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Patent number: 7199607Abstract: There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.Type: GrantFiled: December 22, 2004Date of Patent: April 3, 2007Assignee: Infineon Technologies AGInventors: Ingo Volkening, Hong Lee Koo, Jasmeet Singh Narang, Jiaxiang Shi
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Publication number: 20060132178Abstract: There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.Type: ApplicationFiled: December 22, 2004Publication date: June 22, 2006Inventors: Ingo Volkening, Hong Lee Koo, Jasmeet Singh Narang, Jiaxiang Shi
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Publication number: 20060104315Abstract: There is provided an apparatus and method for ATM bonding. The apparatus comprises a first unit having a first xDSL line connected thereto, a second unit having a second xDSL line connected thereto and a connection between the first unit and the second unit. The first unit is arranged to convert one incoming ATM datastream to a plurality of data and to convert a plurality of incoming data to one ATM data stream. The first unit is arranged to implement the ATM bonding layer of the ATM protocol. The second unit may be arranged to implement one or more of the higher layers.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Applicant: Infineon Technologies AGInventors: Ingo Volkening, Jiaxiang Shi, Chunfeng Hu