Patents by Inventor Jiayin Lu
Jiayin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11436376Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.Type: GrantFiled: May 15, 2019Date of Patent: September 6, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Feifei Yin, Yu Liu, Jiayin Lu
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Patent number: 11216593Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.Type: GrantFiled: May 14, 2019Date of Patent: January 4, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qiang Ding, Yu Liu, Jiayin Lu, ZhuFeng Tan
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Patent number: 10901029Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.Type: GrantFiled: November 14, 2017Date of Patent: January 26, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Feifei Yin, Yu Liu, Jiayin Lu, ZhuFeng Tan
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Patent number: 10489595Abstract: The present invention provide a method and a detection circuit for detecting a security chip operating slate. The detection circuit includes: a first register unit, a triggering unit, a delay unit, a routing unit, and a second register unit, where the second register unit is connected to the triggering unit. A first signal is delayed in the delay unit, to obtain a second signal, a third signal is obtained according to the second signal, and logical operation is performed on the first signal and the third signal, to output a level signal to trigger an alarm unit. Because each unit may be implemented by using a digital circuit, a size of the circuit can be reduced.Type: GrantFiled: November 15, 2017Date of Patent: November 26, 2019Assignee: Huawei Technologies Co., LTD.Inventors: Haofeng Wang, Jiayin Lu, Chongliang Ma
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Publication number: 20190266360Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Inventors: Feifei YIN, Yu LIU, Jiayin LU
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Publication number: 20190266358Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: Qiang Ding, Yu Liu, Jiayin Lu, ZhuFeng Tan
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Publication number: 20190172047Abstract: A system on chip is integrated on a first semiconductor chip, and includes: a system bus, at least one processor coupled to the system bus, and a security processor system coupled to the system bus. The security processor system includes a security processor, a first memory, multiple interfaces, and a security bus, where the security processor, the first memory, and the multiple interfaces are coupled to the security bus, and the security bus is coupled to the system bus. The security processor is configured to execute security operating system software and at least one security software application based on the security operating system software, where the at least one security software application includes mobile payment software used to implement mobile payment. The multiple interfaces include a near field communication (NFC) interface and a biometric recognition input interface.Type: ApplicationFiled: February 5, 2019Publication date: June 6, 2019Applicant: HUAWEI TECHNOLOGIES CO.,LTD.Inventors: Zhufeng Tan, Jiayin Lu, Yu Liu, Shaojie Sun
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Publication number: 20180137283Abstract: The present invention provide a method and a detection circuit for detecting a security chip operating slate. The detection circuit includes: a first register unit, a triggering unit, a delay unit, a routing unit, and a second register unit, where the second register unit is connected to the triggering unit. A first signal is delayed in the delay unit, to obtain a second signal, a third signal is obtained according to the second signal, and logical operation is performed on the first signal and the third signal, to output a level signal to trigger an alarm unit. Because each unit may be implemented by using a digital circuit, a size of the circuit can be reduced.Type: ApplicationFiled: November 15, 2017Publication date: May 17, 2018Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Haofeng WANG, Jiayin LU, Chongliang MA
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Publication number: 20180136274Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.Type: ApplicationFiled: November 14, 2017Publication date: May 17, 2018Inventors: Feifei Yin, Yu Liu, Jiayin Lu, ZhuFeng Tan
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Publication number: 20180137276Abstract: Embodiments of the present disclosure disclose a clock frequency detection method and apparatus. The method includes: dividing a known internal clock frequency range of the system into n frequency intervals, where each frequency interval is corresponding to a frequency detection module, and n is an integer greater than or equal to 2; obtaining a current internal clock frequency of the system, and using the current internal clock frequency as a reference clock frequency; selecting a frequency detection module corresponding to a frequency interval according to the reference clock frequency; and detecting, by the selected frequency detection module, a to-be-detected clock according to a frequency offset range of the reference clock frequency. By using the present disclosure, a risk that an internal clock of the system is attacked may be reduced, and system security may be improved.Type: ApplicationFiled: November 14, 2017Publication date: May 17, 2018Inventors: Qi Su, Jiayin Lu, Yu Liu
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Publication number: 20180114038Abstract: The invention provides a attack prevention method, including: obtaining a first running start condition configured for a cipher engine; configuring, according to the first running start condition, a second running start condition for a scrambling module disposed on the chip, where the second running start condition is used to enable the scrambling module to enter an operating state of generating power consumption and an electromagnetic wave in a process of starting, according to the first running start condition, the cipher engine to perform data encryption/decryption processing; controlling the scrambling module to start to run when the second running start condition is met, where the scrambling module generates the power consumption and the electromagnetic wave during running; and controlling the cipher engine to start when the first running start condition is met, so that the cipher engine starts to perform data encryption/decryption processing.Type: ApplicationFiled: October 25, 2017Publication date: April 26, 2018Inventors: Bo WANG, Jiayin LU, Yu LIU
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Patent number: 9251556Abstract: The present invention provides a display control method and system, and a display device. The method includes acquiring a status value of a display buffer; comparing the status value of the display buffer with a preset warning value of the display buffer; and adjusting a value of a depth of outstanding bus commands according to a comparison result. In the embodiments of the present invention, a status value of the display buffer is compared with a preset warning value of the display buffer, where the status value of the display buffer reflects a change to a current load; it may be determined whether a status value of the display buffer corresponding to the current load is normal according to a comparison result; and a value of a depth of outstanding bus commands is adjusted accordingly, effectively resolve a data real-timeness issue, and ensure that an entire system efficiently runs.Type: GrantFiled: May 24, 2013Date of Patent: February 2, 2016Assignee: Huawei Technologies Co., Ltd.Inventors: Zhe Li, Jun Huang, Jiayin Lu, Jianbo He
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Patent number: 9160895Abstract: An embodiment of the present invention discloses a method for quickly responding to a signal, where the method includes: generating a frame synchronization signal; pre-reading image data, and saving the image data after processing the image data; and receiving a TE signal, and outputting the processed image data according to the TE signal. An embodiment of the present invention further discloses an apparatus for quickly responding to a signal. Using the present invention may improve a rate for responding to a signal and reduce an instantaneous bandwidth pressure on a transmission line.Type: GrantFiled: April 25, 2013Date of Patent: October 13, 2015Assignee: Huawei Technologies Co., Ltd.Inventors: Zhe Li, Kun Wang, Jiayin Lu, Qiwei Liu
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Patent number: 8605893Abstract: An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.Type: GrantFiled: May 7, 2012Date of Patent: December 10, 2013Assignee: China IWNCOMM Co., Ltd.Inventors: Jiayin Lu, Jun Cao, Xiang Yan, Zhenhai Huang
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Publication number: 20130321438Abstract: The present invention provides a display control method and system, and a display device. The method includes acquiring a status value of a display buffer; comparing the status value of the display buffer with a preset warning value of the display buffer; and adjusting a value of a depth of outstanding bus commands according to a comparison result. In the embodiments of the present invention, a status value of the display buffer is compared with a preset warning value of the display buffer, where the status value of the display buffer reflects a change to a current load; it may be determined whether a status value of the display buffer corresponding to the current load is normal according to a comparison result; and a value of a depth of outstanding bus commands is adjusted accordingly, effectively resolve a data real-timeness issue, and ensure that an entire system efficiently runs.Type: ApplicationFiled: May 24, 2013Publication date: December 5, 2013Applicant: Huawei Technologies Co., Ltd.Inventors: Zhe LI, Jun HUANG, Jiayin LU, Jianbo HE
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Patent number: 8570087Abstract: The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.Type: GrantFiled: December 5, 2011Date of Patent: October 29, 2013Assignee: Huawei Technologies Co., Ltd.Inventors: Shiming He, Liqian Chen, Cong Yao, Xiang Li, Yu Liu, Jiayin Lu
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Patent number: 8468286Abstract: A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).Type: GrantFiled: January 14, 2011Date of Patent: June 18, 2013Assignee: Huawei Technologies Co., Ltd.Inventors: Cong Yao, Qiwei Liu, Yu Liu, Xiang Li, Liqian Chen, Shiming He, Jiayin Lu
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Publication number: 20120219149Abstract: An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.Type: ApplicationFiled: May 7, 2012Publication date: August 30, 2012Applicant: China IWNCOMM Co., Ltd.Inventors: JIAYIN LU, JUN CAO, XIANG YAN, ZHENHAI HUANG
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Patent number: 8204218Abstract: An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.Type: GrantFiled: July 19, 2007Date of Patent: June 19, 2012Assignee: China IWNCOMM Co., Ltd.Inventors: Jiayin Lu, Jun Cao, Zhenhai Huang, Xiang Yan
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Publication number: 20120139596Abstract: The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.Type: ApplicationFiled: December 5, 2011Publication date: June 7, 2012Inventors: Shiming He, Liqian Chen, Cong Yao, Xiang Li, Yu Liu, Jiayin Lu