Abstract: A connecting structure for a drill collar of a logging while drilling instrument and drill collar sub male and female joints are provided. The connecting structure for a drill collar of a logging while drilling instrument includes a male connecting joint and a female connecting joint matched with each other. The male connecting joint and the female connecting joint are rotatable relative to each other. Electrical passages are respectively arranged in the male and female connecting joints. One of the male and female connecting joints is provided with a multi-core coaxial electrical male connector connected with the electrical passage, and the other is correspondingly provided with a multi-core coaxial electrical female connector connected with the electrical passage. The male connecting joint is coaxially nested in the female connecting joint. The multi-core coaxial electrical male connector is inserted into and fitted to the multi-core coaxial electrical female connector.

Abstract: A system and method for editing a configuration of a graph executable on a set of configurable assets of a reconfigurable data processor is disclosed. The configurable assets can include processing elements having locations on an integrated circuit and links among the processing elements. The system includes logic to read at least portions of a configuration file in memory. The configuration file can include a topology that maps functions of the graph to the plurality of processing elements and links. The system includes logic to display a graphical interface including graphical objects representing functions mapped to corresponding processing elements and links in a selected portion of the topology. The system includes logic to detect user input identifying a graphical object representing a function mapped to a corresponding processing element or link. The system includes logic to change the topology including mapping of corresponding function.

Abstract: A system and method for editing a configuration of a graph executable on a set of configurable assets of a reconfigurable data processor is disclosed. The configurable assets can include processing elements having locations on an integrated circuit and links among the processing elements. The system includes logic to read at least portions of a configuration file in memory. The configuration file can include a topology that maps functions of the graph to the plurality of processing elements and links. The system includes logic to display a graphical interface including graphical objects representing functions mapped to corresponding processing elements and links in a selected portion of the topology. The system includes logic to detect user input identifying a graphical object representing a function mapped to a corresponding processing element or link. The system includes logic to change the topology including mapping of corresponding function.

Abstract: A connecting structure for a drill collar of a logging while drilling instrument and drill collar sub male and female joints are provided. The connecting structure for a drill collar of a logging while drilling instrument includes a male connecting joint and a female connecting joint matched with each other. The male connecting joint and the female connecting joint are rotatable relative to each other. Electrical passages are respectively arranged in the male and female connecting joints. One of the male and female connecting joints is provided with a multi-core coaxial electrical male connector connected with the electrical passage, and the other is correspondingly provided with a multi-core coaxial electrical female connector connected with the electrical passage. The male connecting joint is coaxially nested in the female connecting joint. The multi-core coaxial electrical male connector is inserted into and fitted to the multi-core coaxial electrical female connector.

Abstract: A horizontal-to-vertical drilling module for a deep well includes a fixed plate (1) provided with a first guide hole having a turning section (11), a core breaking section (13) and a moving section (12); a movable plate (2) movably mounted on one side of the fixed plate and provided with a second guide hole having a turning driving section (21), a core breaking driving section (23) and a moving driving section (22), the projection of the first guide hole on the movable plate intersecting with the second guide hole; a coring module (3) positioned at the other side of the fixed plate and provided with a moving column (31) on the side facing the fixed plate; and a moving slider (4) having an open groove (41), the moving slider being installed in the first guide hole and rotatably connected to the coring module.

Abstract: A horizontal-to-vertical drilling module for a deep well includes a fixed plate (1) provided with a first guide hole having a turning section (11), a core breaking section (13) and a moving section (12); a movable plate (2) movably mounted on one side of the fixed plate and provided with a second guide hole having a turning driving section (21), a core breaking driving section (23) and a moving driving section (22), the projection of the first guide hole on the movable plate intersecting with the second guide hole; a coring module (3) positioned at the other side of the fixed plate and provided with a moving column (31) on the side facing the fixed plate; and a moving slider (4) having an open groove (41), the moving slider being installed in the first guide hole and rotatably connected to the coring module.

Abstract: The present application provides a sidewall coring structure directly driven by an electric motor comprising a drill bit, an electric motor and a speed reducer, the electric motor and the speed reducer are an integrated structure and the drill bit is directly connected to an output of the speed reducer. The coring structure directly drives the drill bit through an integrated structure of the speed reducer and the electric motor; its transmission efficiency is greatly improved, meanwhile the coring structure is more simplified, with improved reliability, easier maintenance and reduced maintenance cost.

Abstract: The present application provides a sidewall coring structure directly driven by an electric motor comprising a drill bit, an electric motor and a speed reducer, the electric motor and the speed reducer are an integrated structure and the drill bit is directly connected to an output of the speed reducer. The coring structure directly drives the drill bit through an integrated structure of the speed reducer and the electric motor; its transmission efficiency is greatly improved, meanwhile the coring structure is more simplified, with improved reliability, easier maintenance and reduced maintenance cost.

Abstract: The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

Abstract: Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes.

Abstract: The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.