Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract: Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor.

Abstract: A semiconductor package stack may include a lower semiconductor package and an upper semiconductor package stacked on a lower package board. The upper semiconductor package may include an upper semiconductor chip mounted on an upper package board with an opening configured to expose a lower surface of the upper semiconductor chip and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of a lower semiconductor chip.

Abstract: A semiconductor package usable with a mobile device includes a circuit board including conductive wirings therein and contact terminals on a rear surface thereof, an integrated circuit chip positioned on a front surface of the circuit board and electrically connected to the conductive wirings, a cover including at least an opening, and to cover the integrated circuit chip such that a flow space is provided around the integrated circuit chip and the opening communicates with the flow space, and an air flow generator positioned on the cover to generate a compulsory air flow through the flow space and the opening, thereby dissipating heat out of the semiconductor package from the integrated circuit chip by the compulsory air flow.

Abstract: A heat spreader is formed on a first semiconductor package and a second semiconductor package adjacent to the first semiconductor package, and first and second thermoelectric modules are included between the first and second semiconductor packages and the heat spreader. The first and second thermoelectric modules are formed to have opposite polarities, and the heat spreader heated by the first thermoelectric module is cooled due to activation of the second thermoelectric module.

Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Abstract: A semiconductor package stack, comprising: a lower semiconductor package including a lower semiconductor chip mounted on a lower package board; an upper semiconductor package stacked on the lower semiconductor package and including an upper semiconductor chip mounted on an upper package board, wherein the upper package board includes an opening configured to expose a lower surface of the upper semiconductor chip; and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of the lower semiconductor chip.

Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.

Abstract: A display device may include a chassis, a flexible printed circuit board on the chassis, a semiconductor device on the flexible printed circuit board, and a supporting element on the flexible printed circuit board. The semiconductor device may be spaced apart from the supporting element. The supporting element may be configured to maintain contact between the chassis and the flexible printed circuit board.

Abstract: In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source.

Abstract: Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor.

Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract: A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Abstract: A display device may include a chassis, a flexible printed circuit board on the chassis, a semiconductor device on the flexible printed circuit board, and a supporting element on the flexible printed circuit board. The semiconductor device may be spaced apart from the supporting element. The supporting element may be configured to maintain contact between the chassis and the flexible printed circuit board.

Abstract: A semiconductor package usable with a mobile device includes a circuit board including conductive wirings therein and contact terminals on a rear surface thereof, an integrated circuit chip positioned on a front surface of the circuit board and electrically connected to the conductive wirings, a cover including at least an opening, and to cover the integrated circuit chip such that a flow space is provided around the integrated circuit chip and the opening communicates with the flow space, and an air flow generator positioned on the cover to generate a compulsory air flow through the flow space and the opening, thereby dissipating heat out of the semiconductor package from the integrated circuit chip by the compulsory air flow.