Abstract: A display substrate, a test method for the display substrate and a display device are provided. The display substrate includes a base substrate, a touch detection circuit layer and a pixel driving circuit layer. The display substrate includes a display region and a non-display region surrounding the display region. The touch detection circuit layer includes a driving signal line and a dummy electrode line arranged side by side in the display region and insulated from each other, and both the driving signal line and the dummy electrode line extend from the display region to the non-display region. The non-display region is provided with a plurality of test pads including a first pad electrically connected to the driving signal line and a second pad electrically connected to the dummy electrode line.

Abstract: A display substrate, a test method for the display substrate and a display device are provided. The display substrate includes a base substrate, a touch detection circuit layer and a pixel driving circuit layer. The display substrate includes a display region and a non-display region surrounding the display region. The touch detection circuit layer includes a driving signal line and a dummy electrode line arranged side by side in the display region and insulated from each other, and both the driving signal line and the dummy electrode line extend from the display region to the non-display region. The non-display region is provided with a plurality of test pads including a first pad electrically connected to the driving signal line and a second pad electrically connected to the dummy electrode line.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

Abstract: The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Abstract: Disclosed are a shift register unit and a method for driving the same, a gate drive circuit, and a display device. The pull-down control circuit in the shift register unit is capable of controlling a potential of a second pull-up node under control of the input signal provided by an input signal terminal. The pull-down circuit is capable of performing noise reduction on a first pull-up node and an output terminal under control of the second pull-up node. Since the potential of the second pull-up node is not pulled up due to the bootstrap effect, the threshold voltages of transistors in the pull-down circuit are less shifted, and the service life of the shift register unit is relatively long.

Abstract: The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.

Abstract: The present disclosure provides a gate driving circuit, a current adjusting method thereof, and a display device. The gate driving circuit includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes an output circuit and a current limiting circuit. The output circuit is configured to output a gate driving signal. The current limiting circuit is electrically connected to the output circuit. The current limiting circuit is configured to limit a current magnitude of the gate driving signal.

Abstract: The present disclosure relates to a display substrate, a display device, and a method for manufacturing a display substrate. The display substrate having a display area and a non-display area, includes: a common electrode layer located in the non-display area; a common electrode line located in the non-display area; and a plurality of bar-shape via holes located in the non-display area; wherein the plurality of bar-shape via holes extend in a direction away from the display area, and the common electrode layer is electrically connected to the common electrode line through the plurality of bar-shape via holes.

Abstract: The present disclosure provides a gate driving circuit, a current adjusting method thereof, and a display device. The gate driving circuit includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes an output circuit and a current limiting circuit. The output circuit is configured to output a gate driving signal. The current limiting circuit is electrically connected to the output circuit. The current limiting circuit is configured to limit a current magnitude of the gate driving signal.

Abstract: The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.

Abstract: Disclosed are a shift register unit and a method for driving the same, a gate drive circuit, and a display device. The pull-down control circuit in the shift register unit is capable of controlling a potential of a second pull-up node under control of the input signal provided by an input signal terminal. The pull-down circuit is capable of performing noise reduction on a first pull-up node and an output terminal under control of the second pull-up node. Since the potential of the second pull-up node is not pulled up due to the bootstrap effect, the threshold voltages of transistors in the pull-down circuit are less shifted, and the service life of the shift register unit is relatively long.

Abstract: The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Abstract: The present disclosure relates to a display substrate, a display device, and a method for manufacturing a display substrate. The display substrate having a display area and a non-display area, includes: a common electrode layer located in the non-display area; a common electrode line located in the non-display area; and a plurality of bar-shape via holes located in the non-display area; wherein the plurality of bar-shape via holes extend in a direction away from the display area, and the common electrode layer is electrically connected to the common electrode line through the plurality of bar-shape via holes.

Abstract: The present disclosure provides a display panel, a display device and a fabrication method thereof. The display panel includes: a first substrate, an opposing substrate opposite to the first substrate, a frame sealant area arranged on edges of the first substrate and edges of the opposing substrate, and a connection part connecting the first substrate with the opposing substrate in the frame sealant area, where the connection part is provided with graphenes for transmitting a first electrical signal of the first substrate to the opposing substrate or for transmitting a second electrical signal of the opposing substrate to the first substrate.

Abstract: An array substrate, a display panel and a manufacturing method thereof, and a display device are disclosed. The array substrate includes a base substrate and a plurality of pixel units which are arrayed on the base substrate; the pixel unit includes a bottom electrode for storage capacitance and a pixel electrode, the pixel electrode and the bottom electrode for storage capacitance are electrically insulated from each other so as to form a storage capacitor; the pixel electrode and the bottom electrode for storage capacitance in the pixel unit are at least partially overlapped with each other in a first direction so as to form the storage capacitance of the pixel unit, in which the first direction is parallel to the base substrate.

Abstract: A thin film transistor device and a method for preparing the same, an array substrate and a display device are disclosed. The thin film transistor device includes a first thin film transistor and a second thin film transistor coupled with each other. A first electrode of the first thin film transistor, a second electrode of the second thin film transistor, and a connecting line therebetween which is configured to couple the first electrode and the second electrode, are formed in a same layer, with each end of the connecting line being connected between respective ends of the first electrode and the second electrode opposite to each other. In the thin film transistor device, the first electrode and the second electrode are spaced apart from each other by a concave portion which is recessed in a region therebetween.

Abstract: A polarizer, a polarizer, a color film substrate, a display panel, and a method of conducting away electrostatic charges are disclosed. The polarizer includes a transparent conductive film layer where the transparent conductive film layer is added with a conductive material, and when the polarizer comprising the transparent conductive film layer connects to a ground, the conductive material that is added to the transparent conductive film layer enables the polarizer to conduct electrostatic charges away from the polarizer to the ground.

Abstract: This disclosure provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes an organic film layer disposed over a substrate, and is provided with a groove, which is configured for positioning a sealant, extends through the organic film layer, and has an opening on a side opposing to the substrate. The array substrate can further include a sealing film, which covers surfaces of the groove to thereby prevent gas release from the organic film layer.

Abstract: A thin film transistor device and a method for preparing the same, an array substrate and a display device are disclosed. The thin film transistor device includes a first thin film transistor and a second thin film transistor coupled with each other. A first electrode of the first thin film transistor, a second electrode of the second thin film transistor, and a connecting line therebetween which is configured to couple the first electrode and the second electrode, are formed in a same layer, with each end of the connecting line being connected between respective ends of the first electrode and the second electrode opposite to each other. In the thin film transistor device, the first electrode and the second electrode are spaced apart from each other by a concave portion which is recessed in a region therebetween.

Abstract: The present disclosure discloses a method for fabricating an array substrate, including: providing a base substrate which includes a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulation layer covering the data electrode pattern layer, the data electrode pattern layer comprising at least one data electrode; forming a via-hole penetrating through the insulation layer so as to expose at least a part of one of the at least one data electrode; forming a transparent electrode material layer; forming a transparent electrode layer which includes a transparent electrode and a connecting portion connected to the transparent electrode, the connecting portion being located in the via-hole so as to electrically connect the transparent electrode with a corresponding data electrode, and a filling being provided above the connecting portion. The present disclosure also discloses an array substrate and a display device.