Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Abstract: A negative voltage level shifter having simplified structure includes a first inverter, a pass unit, a voltage-dividing unit, a second inverter, and a third inverter. The first inverter is powered with a positive supply voltage. Both the second and third inverters are powered with a negative supply voltage. The first inverter inverts an input signal for generating a first internal signal. The pass unit functions to forward the first internal signal to become a second internal signal when the first internal signal has a voltage greater than a threshold voltage. The voltage-dividing unit is employed to generate a third internal signal having a voltage divided from the negative supply voltage and the second internal signal. The second inverter inverts the third internal signal for generating a fourth internal signal. The third inverter inverts the fourth internal signal for generating an output signal.

Abstract: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction and connect to the drain regions of the memory units in the same row. Word lines are arranged in parallel in the column direction and connect to the select gates of the memory units in the same column. Control lines are arranged in parallel in the column direction and connect to the control gates of the memory units in the same column. The control lines are grouped into several groups with n control lines (n is a positive integer not less than 2) in one group, and the control lines in each group are electrically connected to each other.

Abstract: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction and connect to the drain regions of the memory units in the same row. Word lines are arranged in parallel in the column direction and connect to the select gates of the memory units in the same column. Control lines are arranged in parallel in the column direction and connect to the control gates of the memory units in the same column. The control lines are grouped into several groups with n control lines (n is a positive integer not less than 2) in one group, and the control lines in each group are electrically connected to each other.

Abstract: The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively.

Abstract: An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is manufactured with a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic bit in a data program status, a data control circuit electrically connected to the non-volatile memory module for controlling operations of the option fuse circuit, and an output circuit electrically connected to the data control circuit for outputting the logic data bit in a data read status.

Abstract: An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is manufactured with a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic bit in a data program status, a data control circuit electrically connected to the non-volatile memory module for controlling operations of the option fuse circuit, and an output circuit electrically connected to the data control circuit for outputting the logic data bit in a data read status.

Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: A device and method for data sensing includes turning off a first and a second program switches while turning on a first and a second switches in order to output a first current corresponding to a first data from a first memory cell to a biasing circuit, also to output a second current corresponding to a second data from the biasing circuit to a second memory cell, and to charge or discharge a loading node using a difference of the first and the second currents to sense a loading voltage.

Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: A complementary code keying (CCK) demodulation system is disclosed, and more particularly relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. Thus, the operation quantities of correlation calculations are reduced substantially, and the codeword transmitted from transmitter is resolved rapidly, so that the complexity of receiver is decreased and the demodulating speed is speeded up.

Abstract: The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a fourth CMOS transistor and a fifth CMOS transistor.