Patents by Inventor Jie-Hong Wang

Jie-Hong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Universal test platform and test method for latch-up
    Patent number: 7089137
    Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 8, 2006
    Assignee: Faraday Technology Corp.
    Inventors: Jie-Hong Wang, Kai-Jen Ko, An-Ru Cheng
  • UNIVERSAL TEST PLATFORM AND TEST METHOD FOR LATCH-UP
    Publication number: 20050049812
    Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.
    Type: Application
    Filed: May 5, 2004
    Publication date: March 3, 2005
    Inventors: Jie-Hong Wang, Kai-Jen Ko, An-Ru Cheng