Patents by Inventor Jie-Hua Zhao

Jie-Hua Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249599
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 11, 2025
    Assignee: Apple Inc.
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Publication number: 20250046674
    Abstract: A module comprising: a module substrate; a system-on-chip die coupled to the module substrate; a thermal interface material layer coupled to the system-on-chip die; a stiffener structure positioned around the system-on-chip die and coupled to the module substrate; and a lid having a first portion coupled to the thermal interface material layer, a second portion coupled to the stiffener structure and a recessed region formed around the first portion and having a reduced thickness relative to the first portion and the second portion.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Suk-Kyu Ryu, Wei Hu, Jie-Hua Zhao, Myung Jin Yim
  • Publication number: 20240421013
    Abstract: Integrated circuit (IC) structure, IC die structures and methods of fabrication are described in which one or more edge recesses are formed in an IC die. Upon direct bonding to an electronic component, a molding compound can be applied to the bonded structure where the molding compound fills the one or more edge recesses and encroached underneath the IC die and between the IC die and the electronic component.
    Type: Application
    Filed: February 23, 2024
    Publication date: December 19, 2024
    Inventors: Jixuan Gong, Vidhya Ramachandran, Jie-Hua Zhao, Young Doo Jeon, Wei Chen, Jun Zhai
  • Publication number: 20240421126
    Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.
    Type: Application
    Filed: March 7, 2024
    Publication date: December 19, 2024
    Inventors: Chi Nung Ni, Wei Chen, Weiming Chris Chen, Vidhya Ramachandran, Jie-Hua Zhao, Suk-Kyu Ryu, Myung Jin Yim, Chih-Ming Chung, Jun Zhai, Young Doo Jeon, Seungjae Lee
  • Publication number: 20240395686
    Abstract: Electronic packages and electronic systems are described in which a package redistribution layer of the electronic package includes structural features such a via line connections to reduce stress concentration, particularly when the package redistribution layer is formed of organic dielectric materials.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Kunzhong Hu, Arun Sasi, Balaji Nandhivaram Muthuraman, Zezhou Liu
  • Patent number: 12119275
    Abstract: Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 15, 2024
    Assignee: Apple Inc.
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai
  • Publication number: 20240249989
    Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Inventors: Wei Chen, Balaji Nandhivaram Muthuraman, Arun Sasi, Jie-Hua Zhao, Suk-Kyu Ryu, Jun Zhai, Dominic Morache, Young Doo Jeon
  • Publication number: 20240039539
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 11831312
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 28, 2023
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Publication number: 20230317708
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 5, 2023
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Publication number: 20230317624
    Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.
    Type: Application
    Filed: November 28, 2022
    Publication date: October 5, 2023
    Inventors: Wei Chen, Yi Xu, Jie-Hua Zhao, Jun Zhai
  • Publication number: 20230147273
    Abstract: Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.
    Type: Application
    Filed: August 24, 2022
    Publication date: May 11, 2023
    Inventors: Brett W. Degner, Jie-Hua Zhao, Kristopher P. Laurent, Michael E. Leclerc, Rangaraj Dhanasekaran, Simon J. Trivett
  • Patent number: 11646302
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 9, 2023
    Assignee: Apple Inc.
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Publication number: 20230062454
    Abstract: Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai
  • Patent number: 11561144
    Abstract: An electronic device, such as a smart watch, incorporating a fluid-based pressure-sensing device is disclosed. The fluid-based pressure-sensing device includes an enclosure, a pressure sensor, a diaphragm and a sensing medium. The enclosure includes an opening and the pressure sensor is disposed inside the enclosure. The diaphragm hermetically seals the opening, and the sensing medium transfers a pressure exerted on the diaphragm to the pressure sensor. The sensing medium can be liquid oil filling a space of the enclosure, and the diaphragm is a polymer material. The pressure-sensing device may sense an environmental pressure, which may be used by the electronic device to modify its operations, change information that is displayed, and so on.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 24, 2023
    Assignee: APPLE INC.
    Inventors: Caleb C. Han, Brad G. Boozer, Mark G. Walsh, William S. Lee, Tongbi T. Jiang, Jun Zhai, Yun X. Ma, James G. Horiuchi, David MacNeil, Ashwin Balasubramanian, Wei Chen, Jie-Hua Zhao
  • Publication number: 20220231687
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: February 23, 2022
    Publication date: July 21, 2022
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 11309895
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Publication number: 20210305227
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 30, 2021
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Publication number: 20200389172
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 10, 2020
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 10742217
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu