Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A moving state reporting method includes communicating, by a terminal, with a network device using a beam to carry a signal reporting, by the terminal, moving state information of the terminal to the network device, where the moving state information includes a speed flag, and the speed flag indicates that a speed of the terminal exceeds a speed threshold, and receiving, by the terminal, beam management information from the network device.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: The present invention provides a method of evaluating drug resistance in hormone therapy including the following steps. Firstly, a primary level of TRBP in a subject is measured, and an effective amount of tamoxifen, an active form of tamoxifen or an analogous of tamoxifen is provided to the subject. Then, a level of TRBP in the subject is measured after providing tamoxifen, the active form of tamoxifen or the analogous of tamoxifen. Finally, a level change of TRBP in the subject is discriminated to determine a tamoxifen resistance.

Abstract: Disclosed herein is a homogeneous anion exchange membrane produced by subjecting a hydrophilic monomer having an ethylenically unsaturated group to free radical polymerization with a quaternary ammonium salt having an ethylenically unsaturated group, a crosslinking agent, and a photoinitiator. A molar ratio of the hydrophilic monomer to the quaternary ammonium salt is in a range from 1:0.1 to 1:0.7. A biosensing membrane prepared from the homogeneous anion exchange membrane is also disclosed.

Abstract: A moving state reporting method includes communicating, by a terminal, with a network device using a beam to carry a signal reporting, by the terminal, moving state information of the terminal to the network device, where the moving state information includes a speed flag, and the speed flag indicates that a speed of the terminal exceeds a speed threshold, and receiving, by the terminal, beam management information from the network device.

Abstract: The invention belongs to the field of biomedicine, and particularly relates to a glucose core, comprising a glucose and/or a glucose hydrate, a diluent and a binder, wherein, the glucose and/or the glucose hydrate is present in the glucose core in an amount of ?85% by weight percentage; and relates to a glucose pellet comprising the glucose core and a laminated layer coating the glucose core; and further relates to a pharmaceutical composition comprising the glucose pellet. The glucose pellet or the pharmaceutical composition of the invention are useful in treatment and/or assistant treatment of a glycogen storage disease and/or a diabetes.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: The invention belongs to the field of biomedicine, and particularly relates to a glucose core, comprising a glucose and/or a glucose hydrate, a diluent and a binder, wherein, the glucose and/or the glucose hydrate is present in the glucose core in an amount of ?85% by weight percentage; and relates to a glucose pellet comprising the glucose core and a laminated layer coating the glucose core; and further relates to a pharmaceutical composition comprising the glucose pellet. The glucose pellet or the pharmaceutical composition of the invention are useful in treatment and/or assistant treatment of a glycogen storage disease and/or a diabetes.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

Abstract: The present invention provides a method for the detection of the presence of or the risk of breast cancer in a subject is provided. The expression level of snoRNA U50 is detected in a sample isolated from a subject, wherein n decreased expression level of the snoRNA with reference to a normal control indicates the presence of or the risk of breast cancer in the patient from whom the sample was isolated. The present invention further provides a method for predicting the survival time of a patient suffering from a breast cancer and a kit for the detection of the presence of or the risk of breast cancer.

Abstract: The present invention provides a method of evaluating drug resistance in hormone therapy including the following steps. Firstly, a primary level of TRBP in a subject is measured, and an effective amount of tamoxifen, an active form of tamoxifen or an analogous of tamoxifen is provided to the subject. Then, a level of TRBP in the subject is measured after providing tamoxifen, the active form of tamoxifen or the analogous of tamoxifen. Finally, a level change of TRBP in the subject is discriminated to determine a tamoxifen resistance.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.