Patents by Inventor Jie Pu

Jie Pu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250078829
    Abstract: One example method includes receiving an audio stream comprising speech; generating, by automatic speech recognition (“ASR”) software, a plurality of hypotheses, each hypothesis comprising a transcription of a first portion of the speech; rescoring, using a first trained language model, each hypothesis of the plurality of hypotheses; and responsive to a first hypothesis not satisfying a threshold, generating and outputting, using a trained large language model (“LLM”), a final transcription based on the plurality of hypotheses.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Thai Son Nguyen, Jie Pu, Sebastian Stüker
  • Publication number: 20240352790
    Abstract: A manual automatic integrated sunshade panel is provided, the sunshade panel includes a motor, a power storage mechanism, a reel, a curtain connected with the reel, a main control module, and a sensor for recording a rotation stroke of a rotation shaft of the motor, the motor and the sensor are electrically connected with the main control module respectively; a casing or a core body of the power storage mechanism and the motor and are respectively drivingly connected with the reel, or the core body of the power storage mechanism is drivingly connected with the reel and the rotation shaft of the motor is drivingly connected with the core body of the power storage mechanism, and a casing of the motor and the casing of the power storage mechanism maintain relatively stationary. The motor can accurately control the stroke when automatically rolling up and unrolling the curtain.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Xiong Tao Pu, Rui Jie Pu, Shao Tao Pu
  • Patent number: 12048931
    Abstract: The present invention is directed to a foldable transport container suitable to receive and hold multiple plates with samples in it. The container is comfortable to load, transport and unload. The invention also relates to a strip of material for providing such a foldable transport container. Finally the invention relates to a method for assembling such a foldable container.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 30, 2024
    Assignee: Roche Molecular Systems, Inc.
    Inventors: Erich Stiess, Sylvia Dobroszczyk, Jie Pu, Alexander Gaier
  • Patent number: 11937754
    Abstract: A dual-mode water inlet dishwasher includes a shell, an inner container, a spraying arm, a washing pump, a heating washing pump, and a respirator water tank which are provided in the shell. A water trough is provided in the inner container. A water inlet of the water trough is connected to the respirator water tank. A water outlet of the water trough is connected to the heating washing pump. The heating washing pump is connected to the spraying arm. The respirator water tank is provided with a respirator body and a water tank body. A tap water inlet, a water-tank water inlet, and a washing water port are provided on the respirator body or the water tank body. The tap water inlet is connected to tap water by means of a solenoid valve. The water-tank water inlet is connected to the water tank by means of a water pump.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 26, 2024
    Assignee: GUANGDONG JIENUO HOUSEHOLD APPLIANCES CO., LTD.
    Inventors: Jie Pu, Shuntian Yang, Jianhong Shi
  • Publication number: 20230274167
    Abstract: A task learning system includes a knowledge base and a task processing apparatus. The knowledge base is configured to store task attributes and task models corresponding to the task attributes. The task processing apparatus is configured to: obtain an input sample; when an inference task corresponding to the input sample is an unknown task, generate an inference model for the unknown task based on the task attributes and the task models that are stored in the knowledge base module; and perform inference on the input sample by using the inference model to obtain a target inference result.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 31, 2023
    Inventors: Zimu Zheng, Jie Pu, Feng Wang, Jiahao Li
  • Publication number: 20230013072
    Abstract: The present invention is directed to a foldable transport container suitable to receive and hold multiple plates with samples in it. The container is comfortable to load, transport and unload. The invention also relates to a strip of material for providing such a foldable transport container. Finally the invention relates to a method for assembling such a foldable container.
    Type: Application
    Filed: December 21, 2020
    Publication date: January 19, 2023
    Inventors: Erich Stiess, Sylvia Dobroszczyk, Jie Pu, Alexander Gaier
  • Patent number: 11323129
    Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 3, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie Pu, Gangyi Hu, Dongbing Fu, Zhengping Zhang, Liang Li, Ting Li, Daiguo Xu, Mingyuan Xu, Xiaofeng Shen, Xianjie Wan, Youhua Wang
  • Patent number: 11239852
    Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 1, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie Pu, Gangyi Hu, Jian'an Wang, Guangbing Chen, Liang Li, Ting Li, Daiguo Xu, Xingfa Huang, Xi Chen, Tiehu Li, Youhua Wang
  • Publication number: 20220007916
    Abstract: Provided is a dual-mode water inlet dishwasher, comprising a shell, and an inner container, a spraying arm, a washing pump, a heating washing pump, and a respirator water tank which are provided in the shell. A water trough is provided in the inner container. A water inlet of the water trough is connected to the respirator water tank. A water outlet of the water trough is connected to the heating washing pump. The heating washing pump is connected to the spraying arm. The spraying arm sprays water to the inner container. The dishwasher integrates the functions of breathing, dual-mode water channel, anti-overflow and drainage. Also, the dishwasher has the features of simple structure, multi-function, and easy and convenient installation to facilitate the use by users.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 13, 2022
    Inventors: Jie PU, Shuntian YANG, Jianhong SHI
  • Publication number: 20210213455
    Abstract: The present disclosure is directed to a device for supporting manual pipetting of liquids, to the use of such a pipetting support device, and to a method for pipetting liquid, for example from a number of first vessels to a number of second vessels, wherein a moving unit is movable in relation to a first plate and at least partially covers the first plate during use of the pipetting support device, and at least one edge of the moving unit provides guidance to support a manual pipetting procedure from said first plate to said second plate, or vice versa.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 15, 2021
    Inventors: Sylvia Dobroszczyk, Jie Pu
  • Publication number: 20210184689
    Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 17, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Dongbing FU, Zhengping ZHANG, Liang LI, Ting LI, Daiguo XU, Mingyuan XU, Xiaofeng SHEN, Xianjie WAN, Youhua WANG
  • Publication number: 20210135678
    Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 6, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Jian'an WANG, Guangbing CHEN, Liang LI, Ting LI, Daiguo XU, Xingfa HUANG, Xi CHEN, Tiehu LI, Youhua WANG
  • Patent number: 10944390
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 9, 2021
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Dongbing Fu, Shiliu Xu, Tao Liu, Jie Pu, Zhihua Feng
  • Publication number: 20200412353
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Application
    Filed: July 18, 2018
    Publication date: December 31, 2020
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
    Inventors: Daiguo XU, Gangyi HU, Ruzhang LI, Jian'an WANG, Guangbing CHEN, Dongbing FU, Shiliu XU, Tao LIU, Jie PU, Zhihua FENG
  • Publication number: 20200321425
    Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern.
    Type: Application
    Filed: November 7, 2017
    Publication date: October 8, 2020
    Applicants: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Fan YANG, Kun GUO, Jie PU
  • Patent number: 10777635
    Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fan Yang, Kun Guo, Jie Pu
  • Patent number: 10735014
    Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Jie Pu, Gang-yi Hu, Dong-Bing Fu, Xi Chen, Xing-Fa Huang, Yu-Xin Wang, Guang-Bing Chen, Ru-Zhang Li
  • Publication number: 20190355801
    Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern.
    Type: Application
    Filed: November 7, 2017
    Publication date: November 21, 2019
    Applicants: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Fan YANG, Kun GUO, Jie PU
  • Publication number: 20190334538
    Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 31, 2019
    Inventors: JIE PU, GANG-YI HU, DONG-BING FU, XI CHEN, XING-FA HUANG, YU-XIN WANG, GUANG-BING CHEN, RU-ZHANG LI
  • Publication number: 20190219579
    Abstract: Methods and systems for scoring hyaluronan-stained tissue samples by assessing the area of tumor-associated extracellular matrix (ECM) with hyaluronan staining compared to the entire surface area of the relevant portion of the sample. The methods and systems of the present disclosure may be used to, for example, to select patients for receipt of specific treatments.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 18, 2019
    Inventors: Sihem Khelifa, Jie Pu