Patents by Inventor Jiesheng Chen

Jiesheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949681
    Abstract: Methods and systems are provided for improving user authentication and access control by a network file system service in a multi-tenant public cloud environment by receiving a request for a connection to a file system from a file system client (client), sending an identification request for identification authentication of the client to a control system, receiving a response from the control system, establishing the connection to the file system upon determining that the connection to the file system is allowed based on cloud tenant information associated with the client, receiving an attempt to access the file system from the client by a sub-user, authenticating the sub-user based on the cloud tenant information, issuing a security token including a globally unique sub-user identifier of the sub-user, and using the security token to determine access rights of the sub-user to the file system for a subsequent request.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 2, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Qingda Lu, Junpu Chen, Qinghua Ye, Lei Wang, Zhiyong Lin, Liping Bao, Jiesheng Wu, Li Xu, Xiaohui Pei, Feng Zhang, Leilei Tian
  • Patent number: 10522215
    Abstract: A reading circuit is provided in the invention. The reading circuit includes a sensitive amplifier circuit and a latch circuit. A sensitive amplifier circuit is coupled to a first bit line and a second bit line to connect with a storage device, and includes a first inverter and a second inverter. The first bit line is coupled to a source of a first transistor of the first inverter and the second bit line is coupled to a source of a second transistor of the second inverter. The latch circuit is coupled to the sensitive amplifier circuit and outputs an output signal generated by the sensitive amplifier circuit.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 31, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Wenxiao Li, Jiesheng Chen
  • Patent number: 10210916
    Abstract: A reading circuit is provided in the invention. The reading circuit includes a pre-charger, a bit-line selecting circuit, and a latch circuit. The pre-charger receives a pre-charging control signal and the pre-charger is opened or closed according to the pre-charging control signal. The bit-line selecting circuit is coupled with the pre-charger at a node and selects a bit line for reading data according to a selecting signal. The latch circuit is coupled with the pre-charger at a node and outputs and latches the data of the bit line.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Wenxiao Li, Jiesheng Chen
  • Publication number: 20190043542
    Abstract: A reading circuit is provided in the invention. The reading circuit includes a pre-charger, a bit-line selecting circuit, and a latch circuit. The pre-charger receives a pre-charging control signal and the pre-charger is opened or closed according to the pre-charging control signal. The bit-line selecting circuit is coupled with the pre-charger at a node and selects a bit line for reading data according to a selecting signal. The latch circuit is coupled with the pre-charger at a node and outputs and latches the data of the bit line.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 7, 2019
    Inventors: Wenxiao LI, Jiesheng CHEN
  • Publication number: 20190043561
    Abstract: A reading circuit is provided in the invention. The reading circuit includes a sensitive amplifier circuit and a latch circuit. A sensitive amplifier circuit is coupled to a first bit line and a second bit line to connect with a storage device, and includes a first inverter and a second inverter. The first bit line is coupled to a source of a first transistor of the first inverter and the second bit line is coupled to a source of a second transistor of the second inverter. The latch circuit is coupled to the sensitive amplifier circuit and outputs an output signal generated by the sensitive amplifier circuit.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 7, 2019
    Inventors: Wenxiao LI, Jiesheng CHEN
  • Patent number: 9570153
    Abstract: A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word line, and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 14, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Jiesheng Chen, Jieyao Liu