Patents by Inventor Jie-Wei Chen

Jie-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230024220
    Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.
    Type: Application
    Filed: October 5, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Patent number: 11557581
    Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220370606
    Abstract: The present disclosure describes combination therapies and uses thereof for the treatment of cancer. The combinations therapies include at least a first therapeutic agent and a second therapeutic agent.
    Type: Application
    Filed: December 18, 2019
    Publication date: November 24, 2022
    Applicant: Pfizer Inc.
    Inventors: Shih-Hsun CHEN, Luca MICCI, Cecilia Marianne ODERUP, Shahram SALEK-ARDAKANI, Jie WEI
  • Publication number: 20220359642
    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220359490
    Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220352089
    Abstract: A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: HSIEN-WEN LIU, HSIEN-WEI CHEN, JIE CHEN
  • Patent number: 11482649
    Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Publication number: 20220336392
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.
    Type: Application
    Filed: July 3, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Publication number: 20220336329
    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20220302034
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die and a second device die. The first device die includes first bonding pads at a front surface of the first device die. The second device die is bonded on the first device die, and includes die regions and a scribe line region connecting the die regions with one another. The die regions respectively comprise second bonding pads at a front surface of the second device die. The second bonding pads are respectively in contact with one of the first bonding pads.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sung-Feng Yeh
  • Publication number: 20220285324
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a filling material is provided. The first die has a first bonding structure, and the first bonding structure includes first bonding pads and a first heat dissipating element. The second die has a second bonding structure, and the second bonding structure includes second bonding pads and a second heat dissipating element. The first bonding pads are bonded with the second bonding pads. The first heat dissipating element is connected to one first bonding pad of the first bonding pads and the second heat dissipating element is connected to one second bonding pad of the second bonding pads. The filling material is disposed over the first die and laterally around the second die. The first and second dies are bonded through the first and second bonding structures.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220262771
    Abstract: A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11417587
    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11410948
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Publication number: 20220246573
    Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sen-Bor Jan, Sung-Feng Yeh
  • Publication number: 20220246524
    Abstract: A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.
    Type: Application
    Filed: March 2, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Publication number: 20220238397
    Abstract: Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Publication number: 20220230996
    Abstract: A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Publication number: 20220223553
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.
    Type: Application
    Filed: May 10, 2021
    Publication date: July 14, 2022
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Jie Chen
  • Patent number: 11373969
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen