Abstract: A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

Abstract: A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract: A transformer power splitter has a plurality of output ports and an input port. The transformer power splitter includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The secondary winding conductors are electrically connected to the output ports respectively. Each of the secondary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding output port. The primary winding conductors are magnetically coupled to the secondary winding conductors respectively. The primary winding conductors are configured in a topology including series and parallel connections between a positive terminal and a negative terminal of the input port.

Abstract: A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract: A transformer power combiner includes a plurality of current combiners and a voltage combiner. The current combiners are coupled in series, and include a plurality of primary winding conductors magnetically coupled to a plurality of secondary winding conductors respectively. Each of the current combiners is configured to combine currents flowing therethrough. The voltage combiner is coupled to a series connection of the current combiners, and is configured to combine voltages across the current combiners to thereby generate an output of the transformer power combiner.

Abstract: A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract: A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

Abstract: A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

Abstract: A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.

Abstract: A transformer-based circuit has at least a first port and a plurality of second ports. The transformer-based circuit includes a first winding conductor and a plurality of second winding conductors. The first winding conductor is electrically connected to the first port, and has a plurality of sectors connected in series to thereby form a plurality of loops, where the loops are arranged in a concentric-like fashion. The second winding conductors are magnetically coupled to the first winding conductor; besides, the second winding conductors are electrically connected to the second ports, respectively. Overall layout patterns of the second winding conductors are identical to each other. The first winding conductor acts as one of a primary winding conductor and a secondary winding conductor, and each of the second winding conductors acts as the other of the primary winding conductor and the secondary winding conductor.

Abstract: A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.

Abstract: A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.

Abstract: A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract: A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: A transformer-based circuit has at least a first port and a plurality of second ports. The transformer-based circuit includes a first winding conductor and a plurality of second winding conductors. The first winding conductor is electrically connected to the first port, and has a plurality of sectors connected in series to thereby form a plurality of loops, where the loops are arranged in a concentric-like fashion. The second winding conductors are magnetically coupled to the first winding conductor; besides, the second winding conductors are electrically connected to the second ports, respectively. Overall layout patterns of the second winding conductors are identical to each other. The first winding conductor acts as one of a primary winding conductor and a secondary winding conductor, and each of the second winding conductors acts as the other of the primary winding conductor and the secondary winding conductor.

Abstract: A transformer power splitter has a plurality of output ports and an input port. The transformer power splitter includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The secondary winding conductors are electrically connected to the output ports respectively. Each of the secondary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding output port. The primary winding conductors are magnetically coupled to the secondary winding conductors respectively. The primary winding conductors are configured in a topology including series and parallel connections between a positive terminal and a negative terminal of the input port.

Abstract: A transformer power combiner includes a plurality of current combiners and a voltage combiner. The current combiners are coupled in series, and include a plurality of primary winding conductors magnetically coupled to a plurality of secondary winding conductors respectively. Each of the current combiners is configured to combine currents flowing therethrough. The voltage combiner is coupled to a series connection of the current combiners, and is configured to combine voltages across the current combiners to thereby generate an output of the transformer power combiner.